Testing circuit for a memory device

Patent metadata

Field	Value
Publication number	US-12142332-B2
Application number	US-202217939491-A
Country	US
Kind code	B2
Filing date	Sep 7, 2022
Priority date	Sep 14, 2021
Publication date	Nov 12, 2024
Grant date	Nov 12, 2024

Abstract

Methods, systems, and devices for testing circuit for a memory device are described. An apparatus may include a memory system including contacts that route signals to different regions of the memory system. The apparatus may include a first substrate including a memory system interface coupled with the memory system and a probe interface. The apparatus may also include a second substrate coupled with a host system interface of the first substrate and receive the signal of the memory system from the memory system interface. The first interface may route a signal of the memory system to the probe interface and a tester to determine the signal's integrity and any errors associated with the memory system. The first substrate may include a resistor coupled with the contacts of the memory system, the resistor on a surface of the interface may be configured to improve the signal at the tester.

First claim

What is claimed is:

1. An apparatus, comprising:
a memory system comprising contacts configured to route signals to different regions of the memory system;
a first substrate comprising a memory system interface coupled with the memory system and a probe interface, the first substrate configured to route a signal of the memory system to the probe interface, the first substrate comprising a resistor coupled with the contacts of the memory system; and
a second substrate coupled with a host system interface of the first substrate and configured to receive the signal of the memory system from the memory system interface.

2. The apparatus of claim 1 , wherein:
the first substrate further comprises a first surface coupled with the memory system and that includes the memory system interface and the probe interface, the resistor is coupled with the first surface.

3. The apparatus of claim 1 , wherein the resistor is coupled between a first contact of the memory system interface of the first substrate and a second contact of the probe interface.

4. The apparatus of claim 3 , wherein a size of the resistor is based at least in part on an impedance between the first contact and the second contact.

5. The apparatus of claim 1 , wherein:
the contacts are arranged with a pitch; and
a size of the resistor is based at least in part on the pitch of the contacts.

6. The apparatus of claim 1 , further comprising:
a host system associated with the memory system coupled with the second substrate, the second substrate configured to route signals associated with the memory system between the first substrate and the host system.

7. The apparatus of claim 1 , further comprising:
a tester configured to couple with the probe interface and configured to measure the signal routed by the first substrate to the probe interface.

8. The apparatus of claim 7 , wherein the tester is further configured to determine an error associated with the memory system based at least in part on measuring the signal.

9. The apparatus of claim 7 , wherein the resistor is configured to isolate an impedance of the tester from the memory system.

10. The apparatus of claim 1 , wherein the first substrate further comprises a conductive line coupled with the resistor and the probe interface.

11. The apparatus of claim 1 , wherein:
the first substrate comprises a second resistor; and
the resistor has a first resistance the second resistor has a second resistance different than the first resistance.

12. The apparatus of claim 1 , wherein the resistor comprises a surface-mount chip resistor.

13. The apparatus of claim 1 , wherein the resistor comprises a 01005 component.

14. An apparatus, comprising:
a first substrate;
a first interface coupled with a first surface of the first substrate and configured to couple with contacts of a memory system;
a second interface coupled with a second surface of the first substrate and configured to couple with a second substrate that comprises a host system associated with the memory system; and
a third interface coupled with the first surface of the first substrate and coupled with the first interface, the third interface configured to output a signal of the memory system occurring at the contacts, the third interface comprising a resistor coupled with the first surface of the first substrate.

15. The apparatus of claim 14 , wherein the third interface is further configured to couple with a tester and output the signal of the memory system to the tester.

16. The apparatus of claim 15 , wherein the resistor is further configured to isolate an impedance of the tester from the memory system.

17. The apparatus of claim 14 , wherein the third interface comprises a plurality of resistors coupled with the first surface and coupled with the contacts of the memory system.

18. The apparatus of claim 14 , wherein the third interface comprises a conductive line coupled with the resistor and a probe point of the third interface, the signal outputted at the probe point.

19. The apparatus of claim 14 , wherein:
the third interface is configured to comprise a second resistor; and
the resistor has a first resistance the second resistor has a second resistance different than the first resistance.

20. A system, comprising:
a device-under-test comprising:
a memory system;
a first substrate comprising a first interface coupled with the memory system and configured to route a signal of the memory system from the first interface to a second interface of the first substrate and a third interface of the first substrate, the first substrate comprising a resistor on a first surface of the first substrate;
a second substrate coupled with the second interface of the first substrate; and
a host system coupled with the second substrate; and
a tester comprising a probe that is configured to couple with the third interface of the first substrate, the tester configured to measure the signal of the memory system.

21. The system of claim 20 , wherein the resistor is configured to isolate an 2 impedance of the tester from the memory system.

22. The system of claim 20 , wherein the resistor comprises a surface-mount chip resistor.

23. The system of claim 20 , wherein the tester is configured to determine an error associated with the memory system based at least in part on measuring the signal of the memory system.

24. The system of claim 20 , wherein the tester is configured to determine an absence of errors associated with the memory system based at least in part on measuring the signal of the memory system.

25. The system of claim 20 , wherein the second substrate is configured to 2 communicate signals between the host system and the memory system.

Assignees

• Micron Technology Inc

Inventors

• Weng Chunqiang
• Cheng Jingwei

Classifications

• G11C29/1201 Primary

  comprising I/O circuitry · CPC title

• G11C29/025

  in signal lines · CPC title

• G11C2029/5602

  Interface to device under test · CPC title

• G11C29/56 Primary

  External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor · CPC title