Partial block handling protocol in a non-volatile memory device

Patent metadata

Field	Value
Publication number	US-2023386578-A1
Application number	US-202217825439-A
Country	US
Kind code	A1
Filing date	May 26, 2022
Priority date	May 26, 2022
Publication date	Nov 30, 2023
Grant date	—

Abstract

A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device. The block includes a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data. The one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to concurrently program a remaining set of the plurality of wordlines of the block to a threshold voltage.

First claim

What is claimed is:

1 . A system comprising:
a memory device; and a processing device, operatively coupled with the memory device, to perform operations comprising:
initiating a partial block handling protocol for a closed block of the memory device, the block comprising a plurality of wordlines;
sending a first programming command to the memory device to program one or more wordlines of the block with first padding data, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed; and
sending a second programming command to the memory device to concurrently program a remaining set of the plurality of wordlines of the block to a threshold voltage.

2 . The system of claim 1 , wherein initiating the partial block handling protocol comprises:
determining that a predetermined period of time associated with programming the block of the memory device has expired, wherein a first subset of the plurality of wordlines are programmed during the predetermined period of time.

3 . The system of claim 2 , wherein sending the second programming command to the memory device further comprises:
causing a first voltage to be applied to each wordline of the first subset of the plurality of wordlines; causing the first voltage to be applied to each wordline of the one or more wordlines adjacent to the last wordline of the block programmed before the block was closed; and causing a second voltage to be applied to each wordline of the remaining set of the plurality of wordlines of the block to program the remaining set of the plurality of wordlines to the threshold voltage, wherein the second voltage is greater than the first voltage.

4 . The system of claim 2 , wherein initiating the partial block handling protocol further comprises:
responsive to determining that the predetermined period of time has expired, logically closing the block of the memory device to prevent additional program operations from being performed on the block; and determining that the block comprises a second subset of the plurality of wordlines not programmed during the predetermined period of time.

5 . The system of claim 4 , wherein the first subset of the plurality of wordlines comprises the last wordline of the block programmed before the block was closed, and wherein the second subset of the plurality of wordlines comprises (a) the one or more wordlines adjacent to the last wordline of the block programmed before the block was closed and (b) the remaining set of the plurality of wordlines of the block.

6 . The system of claim 1 , wherein the first padding data has a padding data pattern comprising (a) a triple level cell (TLC) data pattern having three bits of data per cell, or (b) a quad-level cell (QLC) data pattern having four bits of data per cell.

7 . The system of claim 1 , wherein sending the second programming command to the memory device further comprises:
causing a voltage pulse to be applied concurrently to each wordline of the remaining set of the plurality of wordlines of the block.

8 . A method comprising:
initiating a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines; sending a first programming command to the memory device to program one or more wordlines of the block with first padding data, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed; and sending a second programming command to the memory device to concurrently program a remaining set of the plurality of wordlines of the block to a threshold voltage.

9 . The method of claim 8 , wherein initiating the partial block handling protocol comprises:
determining that a predetermined period of time associated with programming the block of the memory device has expired, wherein a first subset of the plurality of wordlines are programmed during the predetermined period of time.

10 . The method of claim 9 , wherein sending the second programming command to the memory device further comprises:
causing a first voltage to be applied to each wordline of the first subset of the plurality of wordlines; causing the first voltage to be applied to each wordline of the one or more wordlines adjacent to the last wordline of the block programmed before the block was closed; and causing a second voltage to be applied to each wordline of the remaining set of the plurality of wordlines of the block to program the remaining set of the plurality of wordlines to the threshold voltage, wherein the second voltage is greater than the first voltage.

11 . The method of claim 9 , wherein initiating the partial block handling protocol further comprises:
responsive to determining that the predetermined period of time has expired, logically closing the block of the memory device to prevent additional program operations from being performed on the block; and determining that the block comprises a second subset of the plurality of wordlines not programmed during the predetermined period of time.

12 . The method of claim 11 , wherein the first subset of the plurality of wordlines comprises the last wordline of the block programmed before the block was closed, and wherein the second subset of the plurality of wordlines comprises (a) the one or more wordlines adjacent to the last wordline of the block programmed before the block was closed and (b) the remaining set of the plurality of wordlines of the block.

13 . The method of claim 8 , wherein the first padding data has a padding data pattern comprising (a) a triple level cell (TLC) data pattern having three bits of data per cell, or (b) a quad-level cell (QLC) data pattern having four bits of data per cell.

14 . The method of claim 8 , wherein sending the second programming command to the memory device further comprises:
causing a voltage pulse to be applied concurrently to each wordline of the remaining set of the plurality of wordlines of the block.

15 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
performing a series of programming operations on a block of a memory device for a predetermined period of time, wherein memory cells associated with a first subset of a plurality of wordlines of the block are programmed during the predetermined period of time; upon expiration of the predetermined period of time, determining that a second subset of the plurality of wordlines of the block remain unprogrammed; and performing a padding operation on the block to concurrently program a portion of the second subset of the plurality of wordlines to a threshold voltage.

16 . The non-transitory computer-readable storage medium of claim 15 , wherein the instructions cause the processing device to perform operations further comprising:
upon expiration of the predetermined period of time, logically closing the block of the memory device to prevent additional programming operations from being performed on the block.

17 . The non-transitory computer-readable storage medium of claim 15 , wherein performing the padding operation on the block comprises:
programming one or more wordlines of the second subset with first padding data, wherein the one or more wordlines are adjacent to a last programmed wordline of the first subset.

18 . The non-transitory computer-readable storage medium of claim 17 , wherein performing the padding operation on the b

Assignees

• Micron Technology Inc

Inventors

• Xu Zhongguang
• Xie Tingjun
• Lang Murong

Classifications

• G11C16/102 Primary

  External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C16/3404

  Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells · CPC title