Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2023298641-A1
Application number	US-202217896907-A
Country	US
Kind code	A1
Filing date	Aug 26, 2022
Priority date	Mar 18, 2022
Publication date	Sep 21, 2023
Grant date	—

Abstract

A semiconductor memory device includes a memory cell array, a storing unit that stores data read out from the memory cell array in storage circuits, an output circuit, and a control circuit. In response to a read request, the control circuit adjusts the value of a read pointer of the storing unit, controls the storing unit to sequentially output to the output circuit first and second data stored in first and second storage circuits of the storing unit, respectively, the read pointer having a first value that references the first storage circuit when the first data is output, and a second value that references the second storage circuit when the second data is output, and controls the output circuit to transmit the first and second data to the memory controller as dummy data, and thereafter to transmit at least third data to the memory controller as read data.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a memory cell array; a storing unit configured to temporarily store a plurality of data read out from the memory cell array in a plurality of storage circuits; an output circuit configured to output the data transmitted from the storing unit to an external memory controller; a control circuit configured to control the storing unit to output data to the output circuit in response to a read signal received from the memory controller and in accordance with a value of a read pointer of the storing unit, wherein in response to a request for normal data requested by the memory controller, the control circuit:
adjusts the value of the read pointer,
controls the storing unit to sequentially output to the output circuit at least first and second data stored in first and second storage circuits of the storing unit, respectively, in response to read signals received from the memory controller, the read pointer having a first value that references the first storage circuit when the first data is output, and a second value that references the second storage circuit when the second data is output, and
controls the output circuit to transmit the first data and the second data to the memory controller as non-normal data, and thereafter to transmit at least third data, which is read out from the memory cell array, to the memory controller as the normal data.

2 . The semiconductor memory device according to claim 1 , wherein the value of the read pointer is incremented each time data is output from the storing unit to the output circuit, and the control circuit adjusts the value of the read pointer by decreasing the value thereof.

3 . The semiconductor memory device according to claim 2 , wherein an amount of the decrease in the value of the read pointer corresponds to the number of non-normal data that are to be output from the storing unit to the output circuit.

4 . The semiconductor memory device according to claim 1 , further comprising:
a read pointer generation circuit configured to increment the value of the read pointer in accordance with a clock signal received from the control circuit.

5 . The semiconductor memory device according to claim 4 , wherein
the control circuit is configured to control the storing unit to store data in accordance with a value of a write pointer of the storing unit, and the value of the write pointer is maintained to be the same to prevent new data from being stored in the storing unit when the first and second data are output from the storing unit to the output circuit.

6 . The semiconductor memory device according to claim 5 , wherein
the third data is stored in a third storage circuit of the storing unit, and the value of the write pointer is updated when the third data is transferred from the storing unit to the output circuit, so that fourth data, which is read out from the memory cell array and is part of the normal data, is stored in a fourth storage circuit of the storing unit that is referenced by the updated value of the write pointer.

7 . The semiconductor memory device according to claim 6 , further comprising:
a write pointer generation circuit configured to update the value of the write pointer in accordance with a clock signal received from the control circuit, wherein the clock signal is not supplied to the write pointer generation circuit during a period in which the first and second data are being output from the storing unit to the output circuit.

8 . The semiconductor memory device according to claim 7 , further comprising:
a latency circuit configured to block the clock signal from being supplied to the write pointer generation circuit for a predetermined number of clock cycles.

9 . The semiconductor memory device according to claim 1 , wherein the first data and the second data are different data.

10 . The semiconductor memory device according to claim 1 , wherein the first data that is output as non-normal data and the third data that is output as normal data are the same data.

11 . A method of performing a read operation in a semiconductor memory device in response to a read command received from a memory controller, wherein the semiconductor memory device includes a memory cell array, a storing unit configured to temporarily store a plurality of data read out from the memory cell array in a plurality of storage circuits, and an output circuit configured to output the data transmitted from the storage circuit to the memory controller, said method comprising:
sequentially outputting from the storing unit to the output circuit at least first and second data stored in first and second storage circuits of the storing unit, respectively, in response to read signals received from the memory controller, and in accordance with a value of a read pointer of the storing unit, the read pointer having a first value that references the first storage circuit when the first data is output, and a second value that references the second storage circuit when the second data is output, and transmitting the first data and the second data from the output circuit to the memory controller as non-normal data that is not requested in the read command, and thereafter to transmit at least third data, which is read out from the memory cell array, to the memory controller as normal data that is requested in the read command, wherein the first data and the second data are different data.

12 . The method according to claim 11 , wherein the first data that is output as non-normal data and the third data that is output as normal data are the same data.

13 . The method according to claim 12 , further comprising:
incrementing the value of the read pointer each time data is output from the storing unit to the output circuit.

14 . The method according to claim 13 , further comprising:
prior to outputting the first data, adjusting the value of the read pointer by decreasing the value thereof.

15 . The method according to claim 14 , wherein an amount of the decrease in the value of the read pointer corresponds to the number of non-normal data that are to be output from the storing unit to the output circuit.

16 . The method according to claim 11 , further comprising:
incrementing the value of the read pointer in accordance with a clock signal during a period in which the first data and the second data are output from the storing unit to the output circuit.

17 . The method according to claim 16 , further comprising:
storing data in the storing unit in accordance with a value of a write pointer of the storing unit, wherein the value of the write pointer is maintained to be the same to prevent new data from being stored in the storing unit when the first and second data are output from the storing unit to the output circuit.

18 . The method according to claim 17 , further comprising:
storing the third data in a third storage circuit of the storing unit, and updating the value of the write pointer when the third data is transferred from the storing unit to the output circuit, so that fourth data, which is read out from the memory cell array and is part of the normal data, is stored in a fourth storage circuit of the storing unit that is referenced by the updated value of the write pointer.

19 . The method according to claim 18 , further comprising:
updating the value of the write pointer in accordance with the clock signal, except during a period in which the first and second data are being output from t

Assignees

• Kioxia Corp

Inventors

• Hayashi Shintaro
• Abe Mitsuhiro
• Kanagawa Naoaki

Classifications

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C7/1066

  Output synchronization · CPC title

• G11C2207/2272

  Latency related aspects · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title