Buried via-to-backside power rail (vbpr) for stacked field-effect transistor (fet)

Patent metadata

Field	Value
Publication number	US-2023369217-A1
Application number	US-202217662748-A
Country	US
Kind code	A1
Filing date	May 10, 2022
Priority date	May 10, 2022
Publication date	Nov 16, 2023
Grant date	—

Abstract

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A first field-effect transistor (FET) having a first source/drain region is formed. A second FET having a second source/drain region is formed, where the second FET is stacked above the first FET. A trench extending from above the second source/drain region to beneath the first source/drain region is formed, where the trench passes through portions of (i) the first source/drain region and (ii) the second source/drain region. A bottom contact is formed in the trench. A dielectric layer is formed in the trench, the dielectric layer on a top surface of the bottom contact. A top contact is formed in the trench, the top contact on a top surface of the dielectric layer.

First claim

What is claimed is:

1 . A semiconductor structure comprising:
a first field-effect transistor (FET) having a first source/drain region; a second FET having a second source/drain region, wherein the second FET stacked above the first FET; and a contact region extending from above the second source/drain region to beneath the first source/drain region, wherein:
the contact region passes through portions of (i) the first source/drain region and (ii) the second source/drain region; and
the contact region comprises a top contact, a bottom contact, and a dielectric layer between the top contact and the bottom contact.

2 . The semiconductor structure of claim 1 , wherein a bottom surface of the bottom contact contacts a backside power rail (BPR).

3 . The semiconductor structure of claim 1 , wherein the dielectric layer separates:
the bottom contact from the second source/drain region; and the top contact from the first source/drain region.

4 . The semiconductor structure of claim 1 , wherein the top contact contacts a top surface of the second source/drain region and a sidewall of the second source/drain region.

5 . The semiconductor structure of claim 1 , further comprising a second dielectric layer beneath the first source/drain region.

6 . The semiconductor structure of claim 5 , wherein the bottom contact contacts a bottom surface of the first source/drain region and a sidewall of the first source/drain region.

7 . The semiconductor structure of claim 1 , further comprising a buried oxide layer (BOX) beneath the first FET.

8 . The semiconductor structure of claim 1 , further comprising a top surface of the top contact contacting a back end of line (BEOL) interconnect.

9 . A method of forming a semiconductor structure, the method comprising:
forming a first field-effect transistor (FET) having a first source/drain region; forming a second FET having a second source/drain region, wherein the second FET is stacked above the first FET; forming a trench extending from above the second source/drain region to beneath the first source/drain region, wherein the trench passes through portions of (i) the first source/drain region and (ii) the second source/drain region; forming a bottom contact in the trench; forming a dielectric layer in the trench, the dielectric layer on a top surface of the bottom contact; and forming a top contact in the trench, the top contact on a top surface of the dielectric layer.

10 . The method of claim 9 , wherein the bottom contact contacts a sidewall of the first source/drain region.

11 . The method of claim 9 , wherein the dielectric layer separates:
the bottom contact from the second source/drain region; and the top contact from the first source/drain region.

12 . The method of claim 9 , further comprising: prior to forming the top contact, forming additional material for the second source/drain region by epitaxial growth of a semiconductor material on physically exposed sidewalls of the second source/drain region.

13 . The method of claim 9 , further comprising: prior to forming the top contact, a second trench exposing a top surface of the second source/drain region; and
wherein forming the top contact further comprises, forming the top contact in the second trench.

14 . The method of claim 9 , wherein a top surface of the top contact contacts a back end of line (BEOL) interconnect.

15 . The method of claim 14 , further comprising:
bonding a top surface of the BEOL interconnect to a carrier wafer; flipping the semiconductor structure; and forming a backside power rail (BPR), wherein the BPR contacts a bottom surface of the bottom contact.

16 . The method of claim 9 , wherein forming the first FET and the second FET comprises:
providing a bottom nanosheet stack and a top nanosheet stack separated by a spacer, each nanosheet stack comprising alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet, wherein a dummy gate straddles over the bottom nanosheet stack and the top nanosheet stack; forming a bottom source/drain region by epitaxial growth of a semiconductor material on physically exposed sidewalls of each semiconductor channel material nanosheet of the bottom nanosheet stack, wherein the bottom source/drain region is present on a surface of the dielectric layer; forming an interlayer dielectric layer on the bottom source/drain region; forming a top source/drain region by epitaxial growth of a semiconductor material on physically exposed sidewalls of each semiconductor channel material nanosheet of the top nanosheet stack, wherein the top source/drain region is present on the interlayer dielectric layer; removing the dummy gate; removing each sacrificial semiconductor material nanosheet of the top nanosheet stack and the bottom nanosheet stack to suspend each semiconductor channel material nanosheet of the top nanosheet stack and the bottom nanosheet stack; and forming a functional gate structure in regions occupied by the dummy gate and each sacrificial semiconductor material nanosheet, wherein the functional gate structure wraps around each suspended semiconductor channel material nanosheet.

17 . The method of claim 9 , further comprising:
prior to forming the first source/drain region and the second source/drain region:
recessing exposed portions of a buried oxide layer (BOX) beneath the first FET; and
forming a second dielectric layer in the recess of the BOX.

18 . The method of claim 17 , wherein the bottom contact comprises a dummy contact.

19 . The method of claim 18 , further comprising:
flipping the semiconductor structure; removing the dummy gate; selectively etching expose portions of the second dielectric layer; and forming a metal bottom contact in an area previously occupied by the dummy gate and the selectively etched portions of the second dielectric layer.

20 . The method of claim 19 , further comprising forming a backside power rail (BPR), wherein the BPR contacts a bottom surface of the bottom contact.

Assignees

• IBM

Inventors

• Xie Ruilong
• Lanzillo Nicholas Anthony
• Frougier Julien
• Cheng Kangguo
• Miller Eric
• Clevenger Lawrence A
• Dechene Daniel James

Classifications

• H10P14/3452

  Microstructure · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0257

  comprising using a sacrificial placeholder, e.g. using a sacrificial plug · CPC title