Semiconductor device including a gate insulation pattern and a gate electrode pattern
US-2019067278-A1 · Feb 28, 2019 · US
US2023345708A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2023345708-A1 |
| Application number | US-202217729450-A |
| Country | US |
| Kind code | A1 |
| Filing date | Apr 26, 2022 |
| Priority date | Apr 26, 2022 |
| Publication date | Oct 26, 2023 |
| Grant date | — |
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Methods, apparatuses, and systems related to a sense line and cell contact for a semiconductor structure are described. An example apparatus includes a first source/drain region and a second source/drain region, where the first source/drain region and the second source/drain region are separated by a channel, a gate opposing the channel, a sense line material coupled to the first source/drain region by a cell contact, where the cell contact is made from a combination of a first polysilicon material and a second polysilicon material, and a storage node coupled to the second source/drain region.
Opening claim text (preview).
What is claimed is: 1 . An apparatus, comprising: a first source/drain region and a second source/drain region, wherein the first source/drain region and the second source/drain region are separated by a channel; a gate opposing the channel; a sense line coupled to the first source/drain region by a cell contact, wherein the cell contact is made from a combination of a first polysilicon material and a second polysilicon material; and a storage node coupled to the second source/drain region. 2 . The apparatus of claim 1 , wherein the second polysilicon material that is deposited to make the cell contact has a greater dopant concentration than the first polysilicon material. 3 . The apparatus of claim 2 , wherein a portion of the second polysilicon material that is deposited to make the cell contact is selectively removed prior to depositing a sense line material. 4 . The apparatus of claim 1 , wherein the apparatus is a buried recessed access device (BRAD). 5 . The apparatus of claim 3 , wherein the sense line material has a width from 60 to 80 angstroms. 6 . The apparatus of claim 5 , wherein the sense line material has a height from 250 to 300 angstroms. 7 . The apparatus of claim 3 , wherein the sense line material comprises ruthenium. 8 . The apparatus of claim 1 , wherein at least a portion of dopant of the second polysilicon material is diffused into the first polysilicon material to make a uniformly doped material. 9 . A method, comprising: forming an opening in a semiconductor structure; depositing a first polysilicon material in the opening; depositing a second polysilicon material in the opening on the first polysilicon material, wherein the second polysilicon material has a greater dopant concentration than the first polysilicon material; depositing a mask material on the second polysilicon material; forming a trench in the mask material, the second polysilicon material, and the first polysilicon material; depositing a dielectric material in the trench; removing a portion of the second polysilicon material to make a sense line material deposition space; and depositing a sense line material in the sense line material deposition space. 10 . The method of claim 9 , further comprising conformally depositing a spacer material in the trench prior to depositing the dielectric material in the trench. 11 . The method of claim 10 , further comprising planarizing the spacer material, the mask material, and the dielectric material prior to removing a portion of the second polysilicon material. 12 . The method of claim 9 , further comprising planarizing the sense line material. 13 . The method of claim 12 , further comprising forming a cap material on the planarized sense line material. 14 . The method of claim 13 , wherein the cap material is a nitride material. 15 . The method of claim 9 , wherein the sense line material deposition space has an aspect ratio of about 4. 16 . The method of claim 9 , wherein the first polysilicon material is deposited to a thickness 200 to 450 angstroms. 17 . The method of claim 9 , wherein the second polysilicon material is deposited to a thickness 200 to 450 angstroms. 18 . An apparatus, comprising: a cell contact made from a first polysilicon material and a second first polysilicon material that is formed on the first polysilicon material, wherein the second polysilicon material has a greater dopant concentration than the first polysilicon material; a source/drain region, wherein the cell contact is formed on the source/drain region; and a sense line material, wherein the sense line material is formed on the cell contact. 19 . The apparatus of claim 18 , further comprising a capacitor coupled to the sense line. 20 . The apparatus of claim 18 , wherein the apparatus is s a buried recessed access device (BRAD) that is part of a dynamic random access memory (DRAM) array.
Electricity · mapped topic
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Bit line contacts · CPC title
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