System and method for integrated circuit (ic) nanometer range interconnect fabrication

Patent metadata

Field	Value
Publication number	US-2023326840-A1
Application number	US-202217702293-A
Country	US
Kind code	A1
Filing date	Mar 23, 2022
Priority date	Mar 23, 2022
Publication date	Oct 12, 2023
Grant date	—

Abstract

According to examples, an interconnect system for integrated circuits (ICs) may be fabricated by processing a substrate implanted with copper wells with a photoresist layer such that remaining portions of the photoresist layer expose portions of the copper wells; depositing a barrier layer over a top surface of the wafer, depositing a seed copper layer over the barrier layer; depositing a copper layer over the seed copper layer; planarizing the copper layer and portions of the barrier layer; depositing another copper layer over exposed portions of the substrate, the copper wells, and the interconnect cores; removing portions of the other copper layer between interconnects by processing the second copper layer with another photoresist layer; and removing remaining portions of the other photoresist layer on the interconnects.

First claim

1 . A method to fabricate an interconnect system for an integrated circuit (IC), the method comprising:
fabricating a substrate implanted with copper wells with a first photoresist layer such that remaining portions of the first photoresist layer expose portions of the copper wells; depositing a barrier layer over the exposed portions of the copper wells and the remaining portions of the first photoresist layer; depositing a seed copper layer over the barrier layer; depositing a first copper layer over the seed copper layer; planarizing the first copper layer and portions of the barrier layer such that interconnect cores are exposed over the copper wells; depositing a second copper layer over exposed portions of the substrate, the copper wells, and the interconnect cores; removing portions of the second copper layer between interconnects by processing the second copper layer with a second photoresist layer; and removing remaining portions of the second photoresist layer on the interconnects.

2 . The method of claim 1 , wherein processing the substrate with the first photoresist layer comprises:
depositing the first photoresist layer on the substrate and the copper wells; masking the first photoresist layer with a patterned mask; exposing the masked first photoresist layer to ultra-violet (UV) light; and selectively dissolving unexposed portions of the first photoresist layer.

3 . The method of claim 1 , wherein depositing the barrier layer comprises:
depositing a Tantalum Nitride (TaN) liner by at least one of sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

4 . The method of claim 3 , wherein depositing the seed copper layer comprises:
depositing the seed copper layer on the TaN liner by at least one of sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

5 . The method of claim 4 , wherein a pattern of the TaN liner forms a boundary for the interconnect cores over the copper wells, and depositing the first copper layer over the seed copper layer comprises:
filling the interconnect cores with copper.

6 . The method of claim 1 , wherein planarizing the first copper layer and the portions of the barrier layer comprises:
removing a top portion of the first copper layer and top portions of the barrier layer through chemical-mechanical polishing (CMP).

7 . The method of claim 1 , wherein depositing a second copper layer over the exposed portions of the substrate, the copper wells, and the interconnect cores comprises:
depositing a thick copper profile over the exposed portions of the substrate, the copper wells, and the interconnect cores.

8 . The method of claim 1 , wherein removing the portions of the second copper layer between the interconnects comprises:
depositing the second photoresist layer on the second copper layer; masking the second photoresist layer with a patterned mask; exposing the masked second photoresist layer to ultra-violet (UV) light; selectively dissolving unexposed portions of the second photoresist layer such that the portions of the second copper layer between the interconnects are exposed; and chemically etching the exposed portions of the second copper layer between the interconnects.

9 . The method of claim 8 , further comprising:
selecting one or more of a type or a viscosity of the second photoresist layer based on a particular height of the interconnects.

10 . The method of claim 1 , further comprising:
depositing the first copper layer and the second copper layer by electroplating.

11 . The method of claim 1 , further comprising:
removing exposed portions of the first photoresist layer and the second photoresist layer through chemical etching.

12 . A system to fabricate interconnects for an integrated circuit (IC), the system comprising:
a first photoresist deposition module to cover a substrate implanted with copper wells with a first photoresist layer; a first photoresist pattern and etch module to selectively dissolve the first photoresist layer such that remaining portions of the first photoresist layer expose portions of the copper wells; a barrier layer deposition module to deposit a barrier layer over the exposed portions of the copper wells and the remaining portions of the first photoresist layer; a seed copper layer deposition module to deposit a seed copper layer over the barrier layer; a first copper electroplating module to deposit a first copper layer over the seed copper layer; a copper planarization module to planarize the first copper layer and portions of the barrier layer such that interconnect cores are exposed over the copper wells; a photoresist etch module to remove portions of the first photoresist layer between the interconnect cores; a second copper electroplating module to deposit a second copper layer over exposed portions of the substrate, the copper wells, and the interconnect cores; a second photoresist deposition module to cover second copper layer with a second photoresist layer; a second photoresist pattern and etch module to selectively dissolve portions of the second photoresist layer between the interconnects; a copper chemical etch module to remove portions of the second copper layer between the interconnects; and a residue resist etch module to remove remaining portions of the second photoresist layer on the interconnects.

13 . The system of claim 12 , wherein
the first photoresist deposition module and the second photoresist deposition module are the same module; the first photoresist pattern and etch module and the second photoresist pattern and etch module are the same module; or the first copper electroplating module and the second copper electroplating module are the same module.

14 . The system of claim 12 , wherein the copper planarization module is to planarize the first copper layer and the portions of the barrier layer through chemical-mechanical polishing (CMP).

15 . The system of claim 12 , wherein the second photoresist deposition module is to select one or more of a type or a viscosity of the second photoresist layer based on a particular height of the interconnects.

16 . The system of claim 12 , wherein the barrier layer deposition module is to deposit the barrier layer using Tantalum Nitride (TaN) by at least one of sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

17 . An interconnect apparatus for an integrated circuit (IC) comprising:
a plurality of interconnects on a first layer of a backend of line (BEOL) wafer; a plurality of copper wells in a second layer of the BEOL; a plurality of copper vias in a third layer of the BEOL, the plurality of copper vias coupled to bottom surfaces of corresponding copper wells in the second layer; and a plurality of interconnection lines in one or more additional layers of the BEOL, the plurality of interconnection lines coupled to selected vias in the third layer, wherein:
the plurality of interconnects are supported by a plurality of interconnect cores, and
each interconnect is situated over and coupled to a corresponding copper well.

18 . The interconnect system of claim 17 , wherein the plurality of interconnect cores comprise Tantalum Nitride (TaN) liner walls and are filled with copper.

19 . The interconnect system of claim 17 , wherein the plurality of interconnects are formed through at least two stages of copper electroplating o

Assignees

• Meta Platforms Inc

Inventors

• Pichumani Pradip Sairam
• Rekhi Sandeep
• Byagowi Ahmad

Classifications

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/242

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/01251

  Changing the shapes of bumps · CPC title