Semiconductor device and electronic system including the same

Patent metadata

Field	Value
Publication number	US-2023320097-A1
Application number	US-202318110052-A
Country	US
Kind code	A1
Filing date	Feb 15, 2023
Priority date	Apr 1, 2022
Publication date	Oct 5, 2023
Grant date	—

Abstract

A semiconductor device includes a substrate extending in a first direction and a second direction perpendicular to the first direction, the substrate disposed on a peripheral circuit region and has a cell array region formed therein, a first mold structure which includes insulating layers and gate electrode layers alternately stacked on the substrate, first and second channel structures penetrating, in a third direction perpendicular to the first direction and the second direction, the first mold structure and spaced apart from each other in the first direction, a separation structure penetrating the first mold structure in the third direction between the first and second channel structures and separating the gate electrode layers in the first direction, and first and second auxiliary channel structures penetrating a part of the first mold structure between the separation structure and the first channel structure, and between the separation structure and the second channel structure.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate extending in a first direction and a second direction perpendicular to the first direction, the substrate disposed on a peripheral circuit region and has a cell array region formed therein; a first mold structure which includes insulating layers and gate electrode layers alternately stacked on the substrate; first and second channel structures penetrating, in a third direction perpendicular to the first direction and the second direction, the first mold structure and spaced apart from each other in the first direction; a separation structure penetrating the first mold structure in the third direction between the first and second channel structures and separating the gate electrode layers in the first direction; and first and second auxiliary channel structures penetrating a part of the first mold structure in the third direction between the separation structure and the first channel structure, and between the separation structure and the second channel structure.

2 . The semiconductor device of claim 1 , further comprising:
a common source plate disposed on the substrate below the gate electrode layers and in contact with the first and second channel structures, wherein the first and second auxiliary channel structures penetrate an upper part of the first mold structure and are not in contact with the common source plate.

3 . The semiconductor device of claim 1 , wherein heights of lower ends of the first and second auxiliary channel structures are higher than heights of lower ends of the first and second channel structures.

4 . The semiconductor device of claim 1 , further comprising:
a second mold structure which includes insulating layers and gate electrode layers alternately stacked on the first mold structure, wherein the first and second auxiliary channel structures penetrate the second mold structure.

5 . The semiconductor device of claim 1 , wherein the first and second channel structures are disposed in first and second channel holes each include a blocking film, a charge storage film, a tunnel insulating film, and a semiconductor pattern formed along profiles of first and second channel holes penetrating the first mold structure,
the first and second auxiliary channel structures each include an oxide layer formed along profiles of first and second auxiliary channel holes which penetrate a part of the first mold structure, and diameters of the first and second auxiliary channel holes are smaller than diameters of the first and second channel holes.

6 . The semiconductor device of claim 1 , wherein the first channel structure includes first and second channel patterns which are spaced apart from each other in the second,
the second channel structure includes third and fourth channel patterns spaced apart from each other in the second direction, the separation structure includes first and second separation patterns spaced apart from each other in the second direction between the first and second channel structures, and the first and second auxiliary channel structures include a first auxiliary channel pattern alternately disposed between the first channel pattern and the first separation pattern on the basis of the first direction, and a second auxiliary channel pattern that is spaced apart from the first auxiliary channel pattern in the second direction and alternately disposed between the second channel pattern and the second separation pattern on the basis of the first direction.

7 . The semiconductor device of claim 6 , wherein the first and second separation patterns are merged with each other to form a bar-shaped first extension pattern that extends in the second direction, and a first protrusion pattern that protrudes from the first extension pattern in the first direction.

8 . The semiconductor device of claim 7 , wherein the first and second auxiliary channel patterns and the first and second separation patterns are merged with each other to form a second protrusion pattern that protrudes in the first direction.

9 . The semiconductor device of claim 6 , wherein each of a first distance between the first auxiliary channel pattern and the second auxiliary channel pattern, a second distance between the first auxiliary channel pattern and the first channel pattern, and a third distance between the first auxiliary channel pattern and the first separation pattern is 0.5 times or more and 1.5 times or less than a distance between the first channel pattern and the second channel pattern.

10 . The semiconductor device of claim 6 , wherein each of the first distance between the first auxiliary channel pattern and the second auxiliary channel pattern, the second distance between the first auxiliary channel pattern and the first channel pattern, and the third distance between the first auxiliary channel pattern and the first separation pattern is 0.5 times or more and 1.5 times or less than the distance between the first separation pattern and the second separation pattern.

11 . The semiconductor device of claim 6 , wherein the first channel pattern and the first separation pattern, and the second channel pattern and the second separation pattern are each disposed at the same position on the basis of the second direction, and
the first auxiliary channel pattern is disposed between the first and second channel patterns and between the first and second separation patterns on the basis of the second direction.

12 . A semiconductor device comprising:
a substrate, extending in a first direction and a second direction perpendicular to the first direction, on which a plurality of cell regions, a separation region between the plurality of cell regions, and a dummy region between one of the plurality of cell regions and the separation region are formed; a mold structure which includes insulating layers and gate electrode layers alternately stacked on the substrate; first and second channel structures penetrating, in a third direction perpendicular to the first direction and the second direction, the mold structure and spaced apart from each other in the first direction, in each of the plurality of cell regions; a separation structure penetrating the mold structure in the third direction between the first and second channel structures, in the separation region; and first and second auxiliary channel structures which are spaced apart from each other in the second direction, in the dummy region, wherein each of the first channel structure and the separation structure is disposed between the first and second auxiliary channel structures on the basis of the second direction.

13 . The semiconductor device of claim 12 , wherein the separation structure is disposed at the same position as the first channel structure on the basis of the second direction.

14 . The semiconductor device of claim 12 , wherein the first and second auxiliary channel structures penetrate an upper part of the mold structure and do not come into contact with a bottom surface of the mold structure.

15 . The semiconductor device of claim 12 , wherein the first and second channel structures each include a blocking film, a charge storage film, a tunnel insulating film, and a semiconductor pattern which are formed along profiles of first and second channel holes penetrating the mold structure,
the first and second auxiliary channel structures each include an oxide layer formed along profiles of first and second auxiliary channel holes that penetrate a part of the first mold structure, and diameters of the first and second auxiliary channel h

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Soo Yong
• Kim Jung Min

Classifications

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B41/10

  characterised by the top-view layout · CPC title