Forwarded supply voltage for dynamic voltage and frequency scaling with stacked chip packaging architecture

Patent metadata

Field	Value
Publication number	US-2023245999-A1
Application number	US-202217588392-A
Country	US
Kind code	A1
Filing date	Jan 31, 2022
Priority date	Jan 31, 2022
Publication date	Aug 3, 2023
Grant date	—

Abstract

Embodiments of the present disclosure provide a microelectronic assembly comprising: a first integrated circuit (IC) die in a first layer; an interposer in a second layer not coplanar with the first layer, the first layer coupled to the second layer by interconnects having a pitch of less than 10 micrometers between adjacent interconnects; and a first conductive pathway and a second conductive pathway in the interposer coupling the first IC die and a second IC die. The first IC die is configured to transmit at a first supply voltage through the first conductive pathway to a second IC die, the second IC die is configured to transmit to the first IC die through the second conductive pathway at a second supply voltage simultaneously with the first die transmitting at the first supply voltage, and the first supply voltage is different from the second supply voltage.

First claim

1 . A microelectronic assembly, comprising:
a first integrated circuit (IC) die in a first layer; an interposer in a second layer not coplanar with the first layer, the first layer coupled to the second layer by interconnects having a pitch of less than 10 micrometers between adjacent interconnects; and a first conductive pathway and a second conductive pathway in the interposer coupling the first IC die and a second IC die, wherein:
the first IC die is configured to transmit at a first supply voltage through the first conductive pathway to a second IC die,
the second IC die is configured to transmit to the first IC die through the second conductive pathway at a second supply voltage simultaneously with the first die transmitting at the first supply voltage, and
the first supply voltage is different from the second supply voltage.

2 . The microelectronic assembly of claim 1 , wherein:
the first IC die is configured to transmit at a first supply voltage through the interposer to a plurality of other IC dies, each of the plurality of other IC dies is configured to transmit at respective supply voltages through the interposer to the first IC die simultaneously with the first die transmitting at the first supply voltage, and the respective supply voltages are each different from the first supply voltage.

3 . The microelectronic assembly of claim 1 , wherein:
a first transmission circuit in the first IC die is configured to transmit to a first receiver circuit in the second IC die, and a second receiver circuit in the first IC die is configured to receive from a second transmission circuit in the second IC die.

4 . The microelectronic assembly of claim 3 , wherein:
the first transmission circuit is configured to transmit at a first frequency, the second transmission circuit is configured to transmit at a second frequency, and the first frequency is different from the second frequency.

5 . The microelectronic assembly of claim 3 , wherein a first range of maximum operating frequencies and corresponding supply voltages of the first transmission circuit is different from a second range of maximum operating frequencies and corresponding supply voltages of the second transmission circuit.

6 . The microelectronic assembly of claim 1 , wherein:
the interposer comprises a third IC die, and each of the first conductive pathway and the second conductive pathway is through a metallization stack in the first IC die, at least one of the interconnects, and another metallization stack in the third IC die.

7 . The microelectronic assembly of claim 6 , wherein the interposer further comprises a dielectric material surrounding the third IC die with through-dielectric vias (TDVs) in the dielectric material.

8 . The microelectronic assembly of claim 1 , further comprising the second IC die, wherein:
the second IC die is in the first layer, and each of the first conductive pathway and the second conductive pathway is through a first metallization stack in the first IC die, at least one of the interconnects between the first IC die and the interposer, a second metallization stack in the second IC die, at least one of the interconnects between the second IC die and the interposer, and a third metallization stack in the interposer.

9 . The microelectronic assembly of claim 8 , further comprising a package substrate coupled to the second layer.

10 . The microelectronic assembly of claim 8 , further comprising a package substrate coupled to the first layer.

11 . The microelectronic assembly of claim 1 , wherein the interposer comprises the second IC die.

12 . An interposer, comprising:
a first IC die having a first conductive pathway and a second conductive pathway; a first set of interconnects on a first side, a portion of the first set to couple to a second IC die; and a second set of interconnects on a second side opposite to the first side, wherein:
the first IC die is not coplanar with the second IC die,
the first set of interconnects has a first pitch less than 10 micrometers between adjacent interconnects,
the second set of interconnects has a second pitch greater than 10 micrometers between adjacent ones of the interconnects,
the first conductive pathway is to couple between a first transmission circuit and a first receiver circuit and operate at a first voltage,
the second conductive pathway is to couple between a second transmission circuit and a second receiver circuit and operate at a second voltage different from the first voltage.

13 . The interposer of claim 12 , wherein the first IC die further comprises a plurality of other conductive pathways, each other conductive pathway coupling a respective pair comprising a transmission circuit and a receiver circuit, the other conductive pathways configured to operate at different voltages.

14 . The interposer of claim 12 , wherein:
the first IC die further comprises TSVs, and each of the first conductive pathway and the second conductive pathway is through the TSVs.

15 . The interposer of claim 12 , wherein:
the first transmission circuit and the second receiver circuit are in the first IC die, and the first receiver circuit and the second transmission circuit are in the second IC die.

16 . The interposer of claim 12 , wherein:
another portion of the first set of interconnects is to couple to a third IC die, the third IC die is not coplanar with the first IC die, the first transmission circuit and the second receiver circuit are in the second IC die, and the first receiver circuit and the second transmission circuit are in the third IC die.

17 . The interposer of claim 12 , further comprising a third IC die coplanar with the first IC die, wherein:
the first transmission circuit and the second receiver circuit are in the first IC die, the first receiver circuit and the second transmission circuit are in the third IC die, and each of the first conductive pathway and the second conductive pathway is through the second IC die.

18 . A method for dynamic voltage and frequency scaling (DVFS) in an IC package, the method comprising:
providing a first transmission circuit and a first receiver circuit in a first IC die; providing a second transmission circuit and a second receiver circuit in a second IC die; transmitting a first data signal at a first voltage and a first frequency from the first transmission circuit to the second receiver circuit; and transmitting a second data signal at a second voltage and a second frequency from the second transmission circuit to the first receiver circuit simultaneously as transmitting the first data signal at the first voltage and the first frequency from the first transmission circuit to the second receiver circuit, wherein:
the first voltage is different from the second voltage,
the first frequency is a maximum operating frequency of the first transmission circuit at the first voltage, and
the second frequency is a maximum operating frequency of the second transmission circuit at the second voltage.

19 . The method of claim 18 , further comprising scaling the first voltage in a range between a minimum voltage and a maximum voltage without changing the second voltage.

20 . The method of claim 18 , further comprising:
providing a plurality of transmission circuits in separate IC dies in the IC package; providing a plurality of receiver circuits in the separate IC dies, each one in the plurality of transmission circuits in any one IC die coupled to a correspo

Assignees

• Intel Corp

Inventors

• Pasdast Gerald S
• Wang Peipei
• Elsherbini Adel A

Classifications

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title