Electrostatic discharge protection devices with high current capability

Patent metadata

Field	Value
Publication number	US-2023223395-A1
Application number	US-202217854998-A
Country	US
Kind code	A1
Filing date	Jun 30, 2022
Priority date	Jan 13, 2022
Publication date	Jul 13, 2023
Grant date	—

Abstract

Electrostatic discharge (ESD) protection devices with high current capability are described. The ESD protection device may include a pair of bidirectional diodes (first and second bidirectional diodes) connected in series. Each of the bidirectional diodes includes a low capacitance (LC) diode and a bypass diode connected in parallel. During ESD events, current flows through the LC diode of the first bidirectional diode and the bypass diode of the second bidirectional diode. Particular arrangements of the LC diodes and the bypass diodes are devised to facilitate uniform distribution of the current throughout an area occupied by the ESD protection device.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
an n-type substrate; an n-type layer on the substrate; a p-type layer over the n-type layer, the p-type layer including a surface facing away from the substrate; and a first bidirectional diode including:
a first low capacitance (LC) diode having (1) a first p-type buried region extended from the p-type layer toward the substrate and terminated within the n-type layer and (2) a first n-type region extended from the surface toward the substrate and terminated above the first p-type buried region.

2 . The semiconductor device of claim 1 , wherein the first bidirectional diode further comprises a first isolation structure surrounding the first LC diode, the first isolation structure extended from the surface past an interface between the n-type layer and the substrate.

3 . The semiconductor device of claim 2 , wherein the first bidirectional diode further comprises:
a first bypass diode having a first p-type region extended from the surface toward the substrate and terminated within the p-type layer; and a second isolation structure surrounding the first bypass diode, the second isolation structure extended from the surface past the interface.

4 . The semiconductor device of claim 3 , wherein the first bypass diode lacks the first p-type buried region.

5 . The semiconductor device of claim 3 , further comprising a second bidirectional diode including:
a second LC diode having (1) a second p-type buried region extended from the p-type layer toward the substrate and terminated within the n-type layer and (2) a second n-type region extended from the surface toward the substrate and terminated above the second p-type buried region; a third isolation structure surrounding the second LC diode, the third isolation structure extended from the surface past the interface; a second bypass diode having a second p-type region extended from the surface toward the substrate and terminated within the p-type layer; and a fourth isolation structure surrounding the second bypass diode, the fourth isolation structure extended from the surface past the interface.

6 . The semiconductor device of claim 5 , wherein the substrate provides a common node for the first and second LC diodes and the first and second bypass diodes.

7 . The semiconductor device of claim 5 , further comprising:
a first terminal connected to the first n-type region and the first p-type region of the first bidirectional diode; and a second terminal connected to the second n-type region and the second p-type region of the second bidirectional diode.

8 . The semiconductor device of claim 5 , wherein:
during a first electrostatic discharge (ESD) event with a first polarity, first current flows between the first bypass diode and the second LC diode through a first portion of the substrate under the first LC diode; and during a second ESD event with a second polarity opposite to the first polarity, second current flows between the second bypass diode and the first LC diode through a second portion of the substrate under the second LC diode.

9 . The semiconductor device of claim 1 , wherein the first n-type region is separated from the first p-type buried region by at least two (2) micrometers.

10 . The semiconductor device of claim 1 , wherein:
the first n-type region includes an inner portion with a first average dopant concentration and an outer portion with a second average dopant concentration less than the first average dopant concentration; and the outer portion in contact with the p-type layer forms a first pn junction at a first depth from the surface.

11 . The semiconductor device of claim 10 , wherein:
the first average dopant concentration ranges from 1×10 17 cm −3 to 3×10 19 cm −3 ; and the second average dopant concentration ranges from 1×10 16 cm −3 to 1×10 17 cm −3 .

12 . The semiconductor device of claim 10 , wherein the first p-type buried region includes an interface contacting the n-type layer, the interface forming a second pn junction at a second depth from the surface greater than the first depth.

13 . The semiconductor device of claim 12 , wherein a third pn junction is formed across the p-type layer and the n-type layer at a third depth from the surface greater than the first depth and less than the second depth.

14 . The semiconductor device of claim 1 , wherein:
the n-type substrate has an average dopant concentration greater than 1×10 18 cm −3 ; the n-type layer has an average dopant concentration less than 1×10 16 cm −3 ; the p-type layer has an average dopant concentration less than 1×10 15 cm −3 the p-type buried region has a dopant concentration of at least 1×10 17 cm −3 ; and the p-type region has a dopant concentration of at least 1×10 17 cm −3 .

15 . A semiconductor device, comprising:
an n-type substrate; an n-type layer on the substrate; a p-type layer over the n-type layer, the p-type layer including a surface facing away from the substrate; and a first area including a first side and a second side opposite to the first side, wherein the first area includes (1) a first pn junction at a first depth from the surface, the first pn junction formed across the p-type layer and a first n-type region extended from the surface to the first depth and (2) a second pn junction at a second depth from the surface greater than the first depth, the second pn junction formed across the n-type layer and a first p-type buried region extended from the p-type layer toward the substrate.

16 . The semiconductor device of claim 15 , further comprising:
a first isolation structure surrounding the first area, the first isolation structure extended from the surface past an interface between the n-type layer and the substrate.

17 . The semiconductor device of claim 16 , further comprising:
a second area located proximate to the first side of the first area, the second area including a third pn junction at a third depth from the surface greater than the first depth and less than the second depth, wherein the third pn junction is formed across the p-type layer and the n-type layer; and a second isolation structure surrounding the second area, the second isolation structure extended from the surface past the interface.

18 . The semiconductor device of claim 17 , further comprising:
a third area including a third side and a fourth side opposite to the third side, the third area located proximate to the first area with the fourth side facing the second side, wherein the third area includes (1) a fourth pn junction at the first depth, the fourth pn junction formed across the p-type layer and a second n-type region extended from the surface to the first depth and (2) a fifth pn junction at the second depth, the fifth pn junction formed across the n-type layer and a second p-type buried region extended from the p-type layer toward the substrate; a third isolation structure surrounding the third area, the third isolation structure extended from the surface past the interface; a fourth area located proximate to the third side of the third area, the fourth area including a sixth pn junction at the third depth, wherein the sixth pn junction is formed across the p-type layer and the n-type layer; and a fourth isolation structure surrounding the fourth area, the second isolation structure extended from the surface past the interface.

19 . The semiconductor device of claim 18 , further comprising:
a first terminal connected to the first

Assignees

• Texas Instruments Inc

Inventors

• Kim Sunglyong
• Prasad Sudheer
• S Sreeram N
• Lashkare Sandip
• Kocon Christopher

Classifications

• H10D89/921

  characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses · CPC title

• H10D89/611 Primary

  using diodes as protective elements · CPC title

• H10D89/60 Primary

  Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title

• H10D89/711

  using bipolar transistors as protective elements · CPC title

• H10D89/931

  characterised by the dispositions of the protective arrangements · CPC title