Semiconductor device

Patent metadata

Field	Value
Publication number	US-2023206976-A1
Application number	US-202217875730-A
Country	US
Kind code	A1
Filing date	Jul 28, 2022
Priority date	Dec 24, 2021
Publication date	Jun 29, 2023
Grant date	—

Abstract

A semiconductor device including a substrate; a stack including electrodes and a channel separation pattern, the electrodes being stacked on the substrate and spaced apart from each other, and the channel separation pattern being between adjacent electrodes; and a vertical structure penetrating the stack, wherein the vertical structure includes a conductive pillar, a channel structure, and an interposing layer between the conductive pillar and the channel structure, the channel structure includes first and second channel layers vertically spaced apart from each other by the channel separation pattern, the electrodes include first and second electrodes, which are connected to the first and second channel layers, the channel separation pattern is between the first channel layer and the second channel layer, and the channel separation pattern is between one second electrode that is connected to the first channel layer and one first electrode that is connected to the second channel layer.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate; a stack including electrodes and a channel separation pattern, the electrodes being stacked on the substrate and spaced apart from each other, and the channel separation pattern being between some adjacent ones of the electrodes; and a vertical structure penetrating the stack, wherein: the vertical structure includes a conductive pillar, a channel structure, and an interposing layer between the conductive pillar and the channel structure, the channel structure includes a first channel layer and a second channel layer, which are vertically spaced apart from each other by the channel separation pattern, the electrodes include first electrodes and second electrodes, which are connected to one of the first channel layer and the second channel layer, the channel separation pattern is between the first channel layer and the second channel layer, and the channel separation pattern is between one second electrode that is connected to the first channel layer and one first electrode that is connected to the second channel layer.

2 . The semiconductor device as claimed in claim 1 , wherein the interposing layer includes:
a ferroelectric layer on an outer side surface of the conductive pillar; and a gate insulating layer between the ferroelectric layer and the channel structure.

3 . The semiconductor device as claimed in claim 1 , wherein:
one electrode of the first electrodes and the second electrodes is a source electrode, another one electrode of the first electrodes and the second electrodes is a drain electrode, and a current between the one first electrode and the one second electrode flows through a corresponding one of the first channel layer and the second channel layer that is connected to the one first electrode and the one second electrode.

4 . The semiconductor device as claimed in claim 1 , wherein each of the electrodes includes:
a semiconductor pattern connected to the channel structure; and a pair of horizontal conductive patterns, which are respectively on opposite side surfaces of the semiconductor pattern.

5 . The semiconductor device as claimed in claim 1 , wherein the first channel layer and the second channel layer each independently include a semiconductor material, an amorphous oxide semiconductor material, or a two-dimensional material.

6 . The semiconductor device as claimed in claim 1 , wherein a distance between the first channel layer and the second channel layer is larger than a distance between one second electrode that is connected to the first channel layer and one first electrode that is connected to the second channel layer.

7 . The semiconductor device as claimed in claim 1 , wherein at least a portion of the interposing layer is between the channel separation pattern and the conductive pillar.

8 . The semiconductor device as claimed in claim 1 , further comprising a lower insulating layer between the stack and the substrate,
wherein a bottom surface of the channel structure is at a level between top and bottom surfaces of the lower insulating layer.

9 . The semiconductor device as claimed in claim 1 , wherein:
the electrodes further include third electrodes connected to one of the first channel layer and the second channel layer, the first electrodes and the third electrodes are bit lines, respectively, and the second electrodes are between the first electrodes and the third electrodes and are common source lines.

10 . The semiconductor device as claimed in claim 1 , further comprising a peripheral circuit layer between the stack and the substrate or on the stack.

11 . A semiconductor device, comprising:
a substrate; a lower insulating layer on the substrate; a stack including electrodes stacked on the lower insulating layer and spaced apart from each other; and a vertical structure penetrating the stack, wherein: the vertical structure includes a conductive pillar, a channel structure, and an interposing layer between the conductive pillar and the channel structure, the channel structure is an outermost part of the vertical structure and is connected to the electrodes, and a bottom surface of the channel structure is at a level between a top surface and a bottom surface of the lower insulating layer.

12 . The semiconductor device as claimed in claim 11 , wherein the bottom surface of the channel structure is at a level lower than a bottom surface of the conductive pillar.

13 . The semiconductor device as claimed in claim 11 , wherein:
the lower insulating layer includes a first lower insulating layer, a second lower insulating layer, and a third lower insulating layer, which are sequentially stacked, the second lower insulating layer has an etch selectivity with respect to the first lower insulating layer and the third lower insulating layer, and the bottom surface of the channel structure is at a level between a top surface and a bottom surface of the second lower insulating layer.

14 . The semiconductor device as claimed in claim 11 , wherein a diameter of the conductive pillar is larger than a thickness of each of the electrodes.

15 . The semiconductor device as claimed in claim 11 , wherein each of the electrodes includes:
a semiconductor pattern connected to the channel structure; and a pair of horizontal conductive patterns, which are respectively on opposite side surfaces of the semiconductor pattern.

16 . A semiconductor device, comprising:
a substrate; stacks on the substrate, the stacks being spaced apart from each other in a first direction; and a vertical structure penetrating each of the stacks, wherein: each of the stacks includes a first electrode and a second electrode, which is stacked on the first electrode, the first electrode and the second electrode each extend in a second direction to be parallel to each other, and the vertical structure includes:
a conductive pillar extending in a third direction perpendicular to the first direction and the second direction;
a channel layer connecting the first electrode and the second electrode to each other; and
a ferroelectric layer between the conductive pillar and the channel layer.

17 . The semiconductor device as claimed in claim 16 , wherein:
one of the first electrode and the second electrode is a bit line, another one of the first electrode and the second electrode is a source line, and the conductive pillar is connected to a word line.

18 . The semiconductor device as claimed in claim 16 , wherein the vertical structure further includes a gate insulating layer between the ferroelectric layer and the channel layer.

19 . The semiconductor device as claimed in claim 16 , wherein:
each of the stacks further includes a third electrode, which is stacked on the second electrode and is connected to the channel layer, the first electrode and the third electrode are bit lines, respectively, and the second electrode is between the first electrode and the third electrode and is a common source line.

20 . The semiconductor device as claimed in claim 16 , wherein the channel layer includes a semiconductor material, an amorphous oxide semiconductor material, or a two-dimensional material.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Kyunghwan
• Kim Yongseok
• Kim Hyuncheol
• Park Jongman
• Woo Dongsoo
• Lee Minjun

Classifications

• H10D64/033

  comprising ferroelectric layers · CPC title

• G11C11/2257

  Word-line or row circuits · CPC title

• H01L29/40111

  Electricity · mapped topic

• H01L27/11597

  Electricity · mapped topic

• G11C11/223 Primary

  using MOS with ferroelectric gate insulating film · CPC title