Three-dimensional (3D) ferroelectric dipole metal-oxide semiconductor ferroelectric field-effect transistor (MOSFeFET) system, and related methods and systems

Patent metadata

Field	Value
Publication number	US-9875784-B1
Application number	US-201715486891-A
Country	US
Kind code	B1
Filing date	Apr 13, 2017
Priority date	Apr 13, 2017
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

A three-dimensional (3D) ferroelectric dipole metal-oxide semiconductor ferroelectric field-effect transistor (MOSFeFET) system, and related methods and systems are disclosed. The 3D ferroelectric dipole MOSFeFET system includes a bottom dielectric layer, a gate layer disposed above the bottom dielectric layer, and a top dielectric layer disposed on top of the gate layer. The 3D ferroelectric dipole MOSFeFET system also includes at least one source line (SL) line and at least one bit line (BL). At least one interconnect, which extends between the bottom dielectric layer and the top dielectric layer interconnects the at least one SL with the at least one BL. A ferroelectric dipole MOSFeFET(s) is formed at an intersection area of the at least one interconnect and the gate layer. The 3D ferroelectric dipole MOSFeFET system can lead to improved component density and reduced footprint.

First claim

What is claimed is:

1. A memory system, comprising:
a three-dimensional (3D) ferroelectric dipole metal-oxide semiconductor ferroelectric field-effect transistor (MOSFeFET) system, comprising:
a bottom dielectric layer disposed above a substrate;
at least one source line;
a gate layer disposed above the bottom dielectric layer;
a top dielectric layer disposed above the gate layer;
at least one bit line disposed such that the bottom dielectric layer, the gate layer, and the top dielectric layer are between the at least one source line and the at least one bit line;
at least one interconnect extending between the bottom dielectric layer and the top dielectric layer electrically interconnecting the at least one source line with the at least one bit line; and
at least one ferroelectric dipole MOSFeFET formed at an intersection area of the at least one interconnect and the gate layer.

2. The memory system of claim 1 , wherein the at least one bit line is disposed below the bottom dielectric layer and the at least one source line is disposed above the top dielectric layer perpendicular to the at least one bit line.

3. The memory system of claim 1 , wherein the at least one source line is disposed below the bottom dielectric layer and the at least one bit line is disposed above the top dielectric layer perpendicular to the at least one source line.

4. The memory system of claim 1 , wherein the 3D ferroelectric dipole MOSFeFET system further comprises:
at least one additional dielectric layer disposed above the gate layer;
at least one additional gate layer disposed between the at least one additional dielectric layer and the top dielectric layer;
one or more additional source lines disposed in parallel to the at least one source line;
one or more additional bit lines disposed in parallel to the at least one bit line;
one or more additional interconnects each extending vertically from the bottom dielectric layer to the top dielectric layer electrically interconnecting a respective source line among the one or more additional source lines with a respective bit line among the one or more additional bit lines; and
one or more additional ferroelectric dipole MOSFeFETs formed at one or more intersection areas between the at least one interconnect and the at least one additional gate layer, between the one or more additional interconnects and the gate layer, and between the one or more additional interconnects and the at least one additional gate layer.

5. The memory system of claim 1 , wherein the at least one interconnect comprises at least one cylindrical-shaped through-layer silicon bar, comprising:
a hollow cylinder sidewall having a ferroelectric annulus bounded by an inner circular cylinder corresponding to an inner radius and an outer circular cylinder corresponding to an outer radius larger than the inner radius;
a through-layer silicon bar filling the inner circular cylinder of the hollow cylinder sidewall and coupled to the at least one source line;
a silicon bar-top disposed above the through-layer silicon bar; and
a silicide layer disposed between the silicon bar-top and the at least one bit line.

6. The memory system of claim 5 , wherein the ferroelectric annulus of the hollow cylinder sidewall is formed by a ferroelectric material selected from the group consisting of Hafnium oxide doped with Aluminum (HfAIOx); Hafnium oxide doped with Zirconium (HfZrOx); and Hafnium oxide doped with Silicon (HfSiOx).

7. The memory system of claim 5 , wherein the at least one ferroelectric dipole MOSFeFET comprises:
a gate electrode formed by the gate layer;
a drain electrode formed by the through-layer silicon bar and coupled to the at least one bit line;
a source electrode formed by the through-layer silicon bar and coupled to the at least one source line;
a channel region formed by the through-layer silicon bar between the drain electrode and the source electrode; and
a ferroelectric layer formed by the ferroelectric annulus of the hollow cylinder sidewall between the gate electrode and the channel region.

8. The memory system of claim 7 , further comprising a controller configured to program or erase the at least one ferroelectric dipole MOSFeFET based on an electric field.

9. The memory system of claim 8 , wherein:
the at least one ferroelectric dipole MOSFeFET is at least one n-type ferroelectric dipole MOSFeFET; and
the controller is configured to:
program the at least one n-type ferroelectric dipole MOSFeFET by applying a switching voltage greater than or equal to a positive program voltage between the gate electrode and the source electrode; and
erase the at least one n-type ferroelectric dipole MOSFeFET by applying the switching voltage less than a negative erase voltage between the gate electrode and the source electrode.

10. The memory system of claim 9 , wherein the controller is further configured to keep the drain electrode or the source electrode floating.

11. The memory system of claim 9 , wherein the controller is further configured to apply an equal voltage to the source electrode and the drain electrode.

12. The memory system of claim 8 , wherein:
the at least one ferroelectric dipole MOSFeFET is at least one p-type ferroelectric dipole MOSFeFET; and
the controller is configured to:
program the at least one p-type ferroelectric dipole MOSFeFET by applying a switching voltage less than a negative program voltage between the gate electrode and the source electrode; and
erase the at least one p-type ferroelectric dipole MOSFeFET by applying the switching voltage greater than or equal to a positive erase voltage between the gate electrode and the source electrode.

13. The memory system of claim 12 , wherein the controller is further configured to keep the drain electrode or the source electrode floating.

14. The memory system of claim 12 , wherein the controller is further configured to apply an equal voltage to the source electrode and the drain electrode.

15. The memory system of claim 5 , further comprising the substrate and an isolation layer disposed between the bottom dielectric layer and the substrate.

16. The memory system of claim 5 , wherein:
the through-layer silicon bar comprises a circular cylindrical-shaped via extending vertically from the silicide layer through the gate layer; and
a dielectric film is disposed inside the circular cylindrical-shaped via.

17. The memory system of claim 15 , wherein the 3D ferroelectric dipole MOSFeFET system is an n-type 3D ferroelectric dipole MOSFeFET system, wherein:
the through-layer silicon bar is p-minus (P−) doped;
the silicon bar-top is p-plus (P+) doped;
the at least one source line is p-plus (P+) doped; and
the gate layer is provided as a p-plus (P+) poly layer, a p-type metal gate layer, n-plus (N+) poly layer, or n-type metal gate layer.

18. The memory system of claim 17 , wherein:
the substrate is provided as a p-minus (P−) substrate; and
the isolation layer is provided as an n-minus (N−) well.

19. The memory system of claim 17 , wherein:
the substrate is provided as a p-minus (P−) substrate; and
the isolation layer is provided as an oxide layer.

20. The memory system of claim 15 , wherein the 3D ferroelectric dipole MOSFeFET system is a p-type 3D ferroelectric dipole MOSFeFET system, wherein:
the through-layer silicon bar is n-minus (N−) doped;
the silicon bar-top is n-plus (N+) doped;
the at least one source line is n-plus (N+) doped; and
the gate layer is provided as an n-plus (N+

Assignees

• Qualcomm Inc

Inventors

• Li Xia
• Kang Seung Hyuk
• Yang Bin
• Tao Gengming

Classifications

• G11C11/2275

  Writing or programming circuits or methods · CPC title

• G11C11/223 Primary

  using MOS with ferroelectric gate insulating film · CPC title

• G11C11/2273

  Reading or sensing circuits or methods · CPC title

• H01L27/11597

  Electricity · mapped topic

• H01L27/1159

  Electricity · mapped topic