Contact over active gate structures for advanced integrated circuit structure fabrication

Patent metadata

Field	Value
Publication number	US-2023144607-A1
Application number	US-202318093776-A
Country	US
Kind code	A1
Filing date	Jan 5, 2023
Priority date	Nov 30, 2017
Publication date	May 11, 2023
Grant date	—

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a three-dimensional body comprising silicon; a gate electrode completely surrounding a channel region of the three-dimensional body, the gate electrode having a first side and a second side opposite the first side, a gate insulating cap on the gate electrode, the gate insulating cap having a top surface and a bottom surface; a dielectric spacer adjacent the first side of the gate electrode and adjacent the gate insulating cap; a semiconductor source or drain region adjacent the dielectric spacer; a trench contact structure over the semiconductor source or drain region, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the top surface of the gate insulating cap, and the insulating cap of the trench contact structure having a bottom surface above the bottom surface of the gate insulating cap.

2 . The integrated circuit structure of claim 1 , further comprising:
a conductive via on and electrically connected to a portion of the gate electrode over the three-dimensional body, the conductive via in an opening in the gate insulating cap.

3 . The integrated circuit structure of claim 2 , wherein the conductive via is on a portion of the insulating cap of the trench contact structure but is not electrically connected to the conductive structure of the trench contact structure.

4 . The integrated circuit structure of claim 3 , wherein the conductive via is in an eroded portion of the insulating cap of the trench contact structure.

5 . The integrated circuit structure of claim 2 , further comprising:
a second conductive via on and electrically connected to a portion of the trench contact structure, the second conductive via in an opening of the insulating cap of the trench contact structure.

6 . The integrated circuit structure of claim 5 , wherein the second conductive via is on a portion of the gate insulating cap but is not electrically connected to the gate electrode.

7 . The integrated circuit structure of claim 6 , wherein the second conductive via is in an eroded portion of the gate insulating cap.

8 . An integrated circuit structure, comprising:
a three-dimensional body comprising silicon; a gate electrode completely surrounding a channel region of the three-dimensional body, the gate electrode having a first side and a second side opposite the first side, and having an insulating cap having a top surface; a dielectric spacer adjacent the first side of the gate electrode; a semiconductor source or drain region adjacent the dielectric spacer; a trench contact structure over the semiconductor source or drain region adjacent the dielectric spacer, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating cap of the gate electrode, and the insulating cap of the trench contact structure extending laterally into a recess in the dielectric spacer and overhanging the conductive structure of the trench contact structure.

9 . The integrated circuit structure of claim 8 , further comprising:
a conductive via on and electrically connected to a portion of the gate electrode over the three-dimensional body, the conductive via in an opening in the insulating cap of the gate electrode.

10 . The integrated circuit structure of claim 9 , wherein the conductive via is on a portion of the insulating cap of the trench contact structure but is not electrically connected to the conductive structure of the trench contact structure.

11 . The integrated circuit structure of claim 10 , wherein the conductive via is in an eroded portion of the insulating cap of the trench contact structure.

12 . The integrated circuit structure of claim 8 , further comprising:
a second conductive via on and electrically connected to a portion of the trench contact structure, the second conductive via in an opening of the insulating cap of the trench contact structure.

13 . The integrated circuit structure of claim 12 , wherein the second conductive via is on a portion of the insulating cap of the gate electrode but is not electrically connected to the gate electrode.

14 . The integrated circuit structure of claim 13 , wherein the second conductive via is in an eroded portion of the insulating cap of the gate electrode.

15 . An integrated circuit structure, comprising:
a three-dimensional body comprising silicon; first and second gate electrodes completely surrounding respective first and second channel regions of the three-dimensional body, the first and second gate electrodes each having a first side and a second side opposite the first side, and each having an insulating cap having a top surface; a first dielectric spacer adjacent the first side of the first gate electrode; a second dielectric spacer adjacent the second side of the second gate electrode; a semiconductor source or drain region adjacent the first and second dielectric spacers; a trench contact structure over the semiconductor source or drain region adjacent the first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes, and the insulating cap of the trench contact structure extending laterally into recesses in the first and second dielectric spacers and overhanging the conductive structure of the trench contact structure.

16 . The integrated circuit structure of claim 15 , further comprising:
a conductive via on and electrically connected to a portion of the first gate electrode over the three-dimensional body, the conductive via in an opening in the insulating cap of the first gate electrode.

17 . The integrated circuit structure of claim 16 , wherein the conductive via is on a portion of the insulating cap of the trench contact structure but is not electrically connected to the conductive structure of the trench contact structure.

18 . The integrated circuit structure of claim 17 , wherein the conductive via is in an eroded portion of the insulating cap of the trench contact structure.

19 . The integrated circuit structure of claim 16 , further comprising:
a second conductive via on and electrically connected to a portion of the trench contact structure, the second conductive via in an opening of the insulating cap of the trench contact structure.

20 . The integrated circuit structure of claim 19 , wherein the second conductive via is on a portion of the insulating caps of the first and second gate electrodes but is not electrically connected to the first and second gate electrodes.

21 . The integrated circuit structure of claim 20 , wherein the second conductive via is in an eroded portion of the insulating caps of the first and second gate electrodes.

Assignees

• Intel Corp

Inventors

• Yeoh Andrew W
• Ghani Tahir
• Madhavan Atul
• Hattendorf Michael L
• Auth Christopher P

Classifications

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title