Memory lookup computing mechanisms

US2023101422A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2023101422-A1
Application numberUS-202218060276-A
CountryUS
Kind codeA1
Filing dateNov 30, 2022
Priority dateDec 26, 2017
Publication dateMar 30, 2023
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

According to some example embodiments of the present disclosure, in a method for a memory lookup mechanism in a high-bandwidth memory system, the method includes: using a memory die to conduct a multiplication operation using a lookup table (LUT) methodology by accessing a LUT, which includes floating point operation results, stored on the memory die; sending, by the memory die, a result of the multiplication operation to a logic die including a processor and a buffer; and conducting, by the logic die, a matrix multiplication operation using computation units.

First claim

Opening claim text (preview).

What is claimed is: 1 . A storage system comprising: a first device configured to store matrix data; and a second device configured to: receive intermediate matrix multiplication result data based on the matrix data from the first device; and output a matrix multiplication result based on the intermediate matrix multiplication result data. 2 . The storage system of claim 1 , wherein the first device supports in-memory computing operations. 3 . The storage system of claim 1 , wherein the first device further stores a lookup table, and wherein the first device is further configured to output the intermediate matrix multiplication result data based on the lookup table. 4 . The storage system of claim 1 , wherein the first device corresponds to a first storage device, the storage system further comprising a second storage device distinct from the first storage device. 5 . The storage system of claim 4 , wherein the second storage device comprises dynamic random access memory. 6 . The storage system of claim 1 , wherein the second device is configured to execute an artificial intelligence application based on access to the first device. 7 . A storage device comprising: storage media configured to store matrix data; and an interface configured to send intermediate matrix multiplication result data, based on the matrix data, to a second device configured to output a matrix multiplication result based on the intermediate matrix multiplication result data. 8 . The storage device of claim 7 , wherein the intermediate matrix data is distinct from the matrix data. 9 . The storage device of claim 7 , wherein the storage media supports in-memory computing operations. 10 . The storage device of claim 7 , wherein the storage media further stores a lookup table, and wherein the storage media is further configured to output the intermediate matrix multiplication result data based on the lookup table. 11 . The storage device of claim 7 , wherein the storage media corresponds to a first storage device, the storage device further comprising a second storage device distinct from the first storage device. 12 . The storage device of claim 11 , wherein the second storage device comprises dynamic random access memory. 13 . The storage device of claim 7 , wherein the second device is configured to execute an artificial intelligence application based on access to the storage media. 14 . A method comprising: storing matrix data at a storage device; and sending, from the storage device, intermediate matrix multiplication result data, based on the matrix data, to a second device configured to output a matrix multiplication result based on the intermediate matrix multiplication result data. 15 . The method of claim 14 , wherein the storage device supports in-memory computing operations. 16 . The method of claim 14 , further comprising storing at the storage device a lookup table, and wherein the storage device is further configured to output the intermediate matrix multiplication result data based on the lookup table. 17 . The method of claim 14 , wherein the storage device corresponds to a first storage device, and wherein a second storage device is distinct from the first storage device. 18 . The method of claim 17 , wherein the second storage device comprises dynamic random access memory. 19 . The method of claim 14 , wherein the second device is configured to execute an artificial intelligence application based on access to the storage device. 20 . The method of claim 14 , wherein the intermediate matrix data is distinct from the matrix data. 21 . A method comprising: performing, by a memory device, a first operation using a lookup table (LUT) stored on the memory die; sending, by the memory device, a result of the first operation to a processor device; and performing, by the processor device, a matrix multiplication operation using the result of the first operation performed on the memory device. 22 . The method of claim 21 , wherein the first operation includes a multiplication operation.

Assignees

Inventors

Classifications

  • G06F9/3004Primary

    to perform operations on memory · CPC title

  • G06F7/4876Primary

    Multiplying · CPC title

  • to perform operations on data operands · CPC title

  • Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

  • Methods or arrangements for processing data by operating upon the order or content of the data handled (logic circuits H03K19/00) · CPC title

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Frequently asked questions

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What does patent US2023101422A1 cover?
According to some example embodiments of the present disclosure, in a method for a memory lookup mechanism in a high-bandwidth memory system, the method includes: using a memory die to conduct a multiplication operation using a lookup table (LUT) methodology by accessing a LUT, which includes floating point operation results, stored on the memory die; sending, by the memory die, a result of the…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F9/3004. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Mar 30 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).