Circuits and micro-architecture for a DRAM-based processing unit

Patent metadata

Field	Value
Publication number	US-9922696-B1
Application number	US-201715425996-A
Country	US
Kind code	B1
Filing date	Feb 6, 2017
Priority date	Oct 28, 2016
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

A dynamic random access memory (DRAM) processing unit (DPU) may include at least one computing cell array that may include a plurality of DRAM-based computing cells arranged in an array having at least one column in which the at least one column may include at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first row and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows.

First claim

What is claimed is:

1. A dynamic random access memory (DRAM) based processing unit (DPU), comprising:
at least one computing cell array comprising a plurality of DRAM-based computing cells arranged in an array having at least a first predetermined number of columns and a second predetermined number of rows in which the first predetermined number is greater than or equal to three and the second predetermined number is greater than or equal to three, each column being configured to provide a logic function that operates on a first row and a second row of the column and being configured to store a result of the logic function in a third row of the column, the at least one computing cell array further comprising a third predetermined number of shift lines in which the third predetermined number is two times the first predetermined number, each shift line being coupled to a column of computing cells through at least one corresponding first transistor, the shift lines and the corresponding first transistors being configured to shift contents of two rows of computing cells of a selected column at least two columns in a right direction or in a left direction in the at least one computing cell array.

2. The DPU of claim 1 , wherein the DRAM-based computing cells of at least one column each comprise a three transistor, one capacitor (3T1C) DRAM memory cell.

3. The DPU of claim 2 , wherein the DRAM-based computing cells of at least one column provide a NOR logic function.

4. The DPU of claim 1 , wherein the DRAM-based computing cells of at least one column each comprise a one transistor, one capacitor (1T1C) DRAM memory cell.

5. The DPU of claim 4 , wherein each DRAM-based computing cell further comprises an arithmetic logic unit (ALU) coupled to a bit line of the DRAM-based computing cell, the ALU providing the logic function.

6. The DPU of claim 5 , wherein the ALU provides a NOR logic function.

7. The DPU of claim 1 , further comprising:
at least one data cell array comprising at least one DRAM-based memory cell arranged in the first predetermined number of columns, each column of DRAM-based memory cells of at least one data cell array corresponding to a column of a corresponding computing cell array; and
a sense amplifier coupled to each column of computing cells, each sense amplifier comprising an input that is electrically coupled to a read bit line of the computing cells of the column and an output that is electrically coupled to a write bit line of the computing cells of the column.

8. A dynamic random access memory (DRAM) based processing unit (DPU), comprising:
at least one computing cell array comprising a plurality of DRAM-based computing cells arranged in an array having at least a first predetermined number of columns and a second predetermined number of rows in which the first predetermined number is greater than or equal to three and the second predetermined number is greater than or equal to three, each column being configured to provide a logic function that operates on a first row and a second row of the column and being configured to store a result of the logic function in a third row of the column, the at least one computing cell array further comprising a third predetermined number of shift lines in which the third predetermined number is two times the first predetermined number, each shift line being coupled to a column of computing cells through at least one corresponding first transistor, the shift lines and the corresponding first transistors being configured to shift contents of two rows of computing cells of a selected column at least two columns in a right direction or in a left direction in the at least one computing cell array; and
at least one data cell array comprising at least one DRAM-based memory cell arranged in the first predetermined number of columns and at least one row, each column of DRAM-based memory cells of at least one data cell array corresponding to a column of a corresponding computing cell array.

9. The DPU of claim 8 , wherein the DRAM-based computing cells of at least one column each comprise a three transistor, one capacitor (3T1C) DRAM memory cell.

10. The DPU of claim 9 , wherein the DRAM-based computing cells of at least one column provide a NOR logic function.

11. The DPU of claim 8 , wherein the DRAM-based computing cells of at least one column each comprise a one transistor, one capacitor (1T1C) DRAM memory cell.

12. The DPU of claim 11 , wherein each DRAM-based computing cell further comprises an arithmetic logic unit (ALU) coupled to a bit line of the DRAM-based computing cell, the ALU providing the logic function.

13. The DPU of claim 12 , wherein the ALU provides a NOR logic function.

14. A dynamic random access memory (DRAM) based processing unit (DPU), comprising:
at least one data cell array comprising at least one DRAM-based memory cell arranged in a first predetermined number of columns and at least one row, the first predetermined number of columns being greater than or equal to three;
at least one computing cell array comprising a plurality of DRAM-based computing cells each computing cell array corresponding to each data cell array and being arranged in an array having the first predetermined number of columns and a second predetermined number of rows in which the second predetermined number is greater than or equal to three, each column of computing cells being configured to provide a logic function that operates on a first row and a second row of the column of computing cells and being configured to store a result of the logic function in a third row of the column of computing cells, the at least one computing cell array further comprising a third predetermined number of shift lines in which the third predetermined number is two times the first predetermined number, each shift line being coupled to a column of computing cells through at least one corresponding first transistor, the shift lines and the corresponding first transistors being configured to shift contents of two rows of computing cells of a selected column at least two columns in a right direction or in a left direction in the at least one computing cell array;
a sense amplifier coupled to each column of computing cells, each sense amplifier comprising an input that is electrically coupled to a read bit line of the computing cells in a column of computing cells and an output that is electrically coupled to a write bit line of the computing cells of the column of computing cells; and
a decoder electrically coupled to each computing cells, the decoder receiving DRAM-based address signals corresponding to instructions to select the computing cells of the column to generate the logic function on the first and second rows of the column and to store the result of the logic function in the third row of the column.

15. The DPU of claim 14 , wherein the DRAM-based computing cells of at least one column each comprise a three transistor, one capacitor (3T1C) DRAM memory cell.

16. The DPU of claim 15 , wherein the DRAM-based computing cells of at least one column provide a NOR logic function.

17. The DPU of claim 14 , wherein the DRAM-based computing cells of at least one column each comprise a one transistor, one capacitor (1T1C) DRAM memory cell.

18. The DPU of claim 17 , wherein each DRAM-based computing cell further comprises an arithmetic logic unit (ALU) coupled to a bit line of the DRAM-based computing cell, the ALU providing a NOR logic function.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Li Shaungchen
• Niu Dimin
• Malladi Krishna
• Zheng Hongzhong

Classifications

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title