Ruthenium-based liner for a copper interconnect

Patent metadata

Field	Value
Publication number	US-2023068398-A1
Application number	US-202117446398-A
Country	US
Kind code	A1
Filing date	Aug 30, 2021
Priority date	Aug 30, 2021
Publication date	Mar 2, 2023
Grant date	—

Abstract

In some implementations, one or more semiconductor processing tools may form a via within a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a ruthenium-based liner within the via. The one or more semiconductor processing tools may deposit, after depositing the ruthenium-based liner, a copper plug within the via.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, comprising:
forming a via within a substrate of the semiconductor device; depositing a ruthenium-based liner within the via; and depositing, after depositing the ruthenium-based liner, a copper plug within the via.

2 . The method of claim 1 , further comprising:
depositing, before depositing the ruthenium-based liner within the via, a tantalum nitride-based liner within the via,
wherein depositing the ruthenium-based liner within the via comprises depositing the ruthenium-based liner on the tantalum nitride-based liner.

3 . The method of claim 1 , further comprising:
depositing, before depositing the copper plug within the via, a cobalt-based liner within the via,
wherein depositing the copper plug within the via comprises depositing the copper plug on the cobalt-based liner.

4 . The method of claim 1 , wherein depositing the copper plug within the via comprises:
depositing copper material within the via and on an upper surface of the semiconductor device, and
performing, after depositing the copper material, a chemical-mechanical polishing process to remove the copper material from the upper surface of the semiconductor device.

5 . The method of claim 1 , further comprising:
depositing, after depositing the copper plug, a ruthenium cap on an upper surface of the via.

6 . The method of claim 5 , further comprising:
performing, before depositing the ruthenium cap and after performing a chemical-mechanical polishing process on an upper surface of the copper plug, a pre-cleaning operation on an upper surface of the semiconductor device.

7 . The method of claim 6 , wherein performing the pre-cleaning operation comprises application of one or more of hydrogen or ammonia plasma.

8 . The method of claim 5 , further comprising:
applying, before depositing the ruthenium cap, a surfactant material to an upper surface of the substrate,
wherein the surfactant material is configured to react with the substrate to resist deposition of ruthenium material on the upper surface of the substrate.

9 . The method of claim 5 , further comprising:
applying, before depositing the ruthenium cap, one or more of methanol or a hydrogen soak to an upper surface of the substrate,
wherein the one or more of the methanol or the hydrogen soak are configured to react with the substrate to resist deposition of ruthenium material on the upper surface of the substrate.

10 . The method of claim 5 , further comprising:
depositing a cobalt cap on an upper surface of the ruthenium cap.

11 . The method of claim 1 , wherein depositing the copper plug comprises:
depositing the copper plug using a reflow deposition operation.

12 . A semiconductor device, comprising:
a via within a substrate of the semiconductor device; a ruthenium-based liner disposed within the via; and a copper plug disposed on the ruthenium-based liner within the via.

13 . The semiconductor device of claim 12 , further comprising:
a ruthenium cap disposed on the copper plug.

14 . The semiconductor device of claim 13 , further comprising:
a cobalt cap disposed on the ruthenium cap.

15 . The semiconductor device of claim 13 , further comprising:
a tantalum nitride-based barrier disposed on the substrate within the via,
wherein the ruthenium-based liner is disposed within the via on the tantalum nitride-based barrier.

16 . The semiconductor device of claim 12 , wherein the ruthenium-based liner comprises ruthenium material and cobalt material.

17 . A semiconductor device, comprising:
a via within a substrate of the semiconductor device; a liner, comprising ruthenium material and cobalt material, disposed within the via; and a copper plug disposed on at least a portion of the liner.

18 . The semiconductor device of claim 17 , further comprising:
a cobalt cap disposed on the copper plug.

19 . The semiconductor device of claim 17 , wherein the copper plug is in contact with the ruthenium material and the cobalt material.

20 . The semiconductor device of claim 17 , further comprising:
a tantalum nitride-based barrier disposed on the substrate within the via,
wherein the liner is disposed within the via on the tantalum nitride-based barrier.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Yao-Min
• Gao ming-yuan
• Chiang Ming-Chou
• Chin Shu-Cheng
• Hsieh Huei-Wen
• Kuo Kai-Shiang
• Lin Yen-Chun
• Weng Cheng-Hui
• Lin Chun-Chieh
• Su Hung-Wen

Classifications

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10W20/425 Primary

  Barrier, adhesion or liner layers · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title