Semiconductor device

Patent metadata

Field	Value
Publication number	US-2022416055-A1
Application number	US-202217898544-A
Country	US
Kind code	A1
Filing date	Aug 30, 2022
Priority date	May 18, 2020
Publication date	Dec 29, 2022
Grant date	—

Abstract

A semiconductor device includes: a first electrode; a second electrode; and a dielectric layer stack positioned between the first electrode and the second electrode, the dielectric layer stack including a first anti-ferroelectric layer, a second anti-ferroelectric layer, and a ferroelectric layer between the first anti-ferroelectric layer and the second anti-ferroelectric.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first electrode; a second electrode; an alternating stack that is positioned between the first electrode and the second electrode, the alternating stack including a plurality of dielectric layer stacks and a plurality of leakage blocking layers that are alternately stacked, an interface layer disposed between the second electrode and the alternating stack; and an additional interface layer disposed between the first electrode and the alternating stack, wherein each of the dielectric layer stacks includes a first anti-ferroelectric layer, a second anti-ferroelectric layer, and a ferroelectric layer disposed between the first anti-ferroelectric layer and the second anti-ferroelectric layer.

2 . The semiconductor device of claim 1 , wherein the first anti-ferroelectric layer, the ferroelectric layer, and the second anti-ferroelectric layer are vertically arranged between the first electrode and the second electrode.

3 . The semiconductor device of claim 1 , wherein the first anti-ferroelectric layer and the second anti-ferroelectric layer include an anti-ferroelectric hafnium zirconium oxide, and the ferroelectric layer includes a ferroelectric hafnium zirconium oxide.

4 . The semiconductor device of claim 1 , wherein the first anti-ferroelectric layer and the second anti-ferroelectric layer include a hafnium zirconium oxide having a zirconium content greater than a hafnium content.

5 . The semiconductor device of claim 1 , wherein the ferroelectric layer includes a hafnium zirconium oxide whose hafnium content and zirconium content are the same.

6 . The semiconductor device of claim 1 , wherein the first anti-ferroelectric layer and the second anti-ferroelectric layer include PbZrO 3 , PbHfO 3 , PbMgWO 3 , PbZrTiO 3 , BiNaTiO 3 or NaNbO 3 .

7 . The semiconductor device of claim 1 , wherein the ferroelectric layer includes BaTiO 3 , PbTiO 3 , BiFeO 3 , SrTiO 3 , PbMgNdO 3 , PbMgNbTiO 3 , PbZrNbTiO 3 , PbZrTiO 3 , KNbO 3 , LiNbO 3 , GeTe, LiTaO 3 , KNaNbO 3 , or BaSrTiO 3 .

8 . The semiconductor device of claim 1 , wherein the interface layer includes a material that is reduced prior to the dielectric layer stack.

9 . The semiconductor device of claim 1 , wherein the interface layer and the additional interface layer include a material having a greater electronegativity than the first and second anti-ferroelectric layers and the ferroelectric layer.

10 . The semiconductor device of claim 1 , wherein the interface layer and the additional interface layer include titanium oxide, tantalum oxide, niobium oxide, or tin oxide.

11 . The semiconductor device of claim 1 , wherein the first electrode includes a cylinder shape, a pillar shape, or a hybrid pillar-cylinder.

12 . The semiconductor device of claim 1 , further comprising:
a semiconductor substrate including a first doped region and a second doped region; a word line buried in a semiconductor substrate between the first doped region and the second doped region; a bit line formed over the word line and coupled to the first doped region; and a storage node contact plug coupled to the second doped region, wherein the first electrode is electrically connected to the storage node contact plug.

13 . The semiconductor device of claim 1 , wherein the first electrode, the alternating stack, and the second electrode form a Dynamic Random Access Memory (DRAM) capacitor.

14 . The semiconductor device of claim 1 , wherein each of the leakage blocking layers includes a material having a higher energy band gap than the dielectric stack.

15 . The semiconductor device of claim 1 , wherein each of the leakage blocking layers includes a material having a higher energy band gap than the first anti-ferroelectric layer, the second anti-ferroelectric layer, and the ferroelectric layer.

16 . The semiconductor device of claim 1 , wherein each of the leakage blocking layers includes aluminum oxide or beryllium oxide.

17 . The semiconductor device of claim 1 , wherein the interface layer includes a stack of molybdenum and molybdenum nitride (Mo/MoN) or a stack of tungsten and tungsten nitride (W/WN).

18 . The semiconductor device of claim 1 , further comprising:
a supporter for supporting of the first electrode.

Assignees

• Sk Hynix Inc

Inventors

• Maeng Wan Joo
• Jin Hyun Soo
• Kang Se Hun
• Im Ki Vin
• Yoon Kyoung Ryul

Classifications

• H01L27/11502

  Electricity · mapped topic

• H01L27/11585

  Electricity · mapped topic

• H01L29/516 Primary

  Electricity · mapped topic

• H01L29/40111

  Electricity · mapped topic

• H01L28/56

  Electricity · mapped topic