Ferroelectric finfet

Patent metadata

Field	Value
Publication number	US-2016358915-A1
Application number	US-201615238023-A
Country	US
Kind code	A1
Filing date	Aug 16, 2016
Priority date	Mar 6, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

A semiconductor device includes a semiconductor substrate and a fin positioned above the semiconductor substrate, wherein the fin includes a semiconductor material. Additionally, a ferroelectric high-k spacer covers sidewall surfaces of the fin and a non-ferroelectric high-k material layer covers the ferroelectric high-k spacer and the fin, wherein a portion of the non-ferroelectric high-k material layer is positioned on and in direct contact with the semiconductor material at the upper surface of the fin.

First claim

What is claimed:

1 . A semiconductor device, comprising:
a semiconductor substrate; a fin positioned above said semiconductor substrate, said fin comprising a semiconductor material; a ferroelectric high-k spacer covering sidewall surfaces of said fin; and a non-ferroelectric high-k material layer covering said ferroelectric high-k spacer and said fin, wherein a portion of said non-ferroelectric high-k material layer is positioned on and in direct contact with said semiconductor material at an upper surface of said fin.

2 . The semiconductor device of claim 1 , wherein said non-ferroelectric high-k material layer extends continuously over said ferroelectric high-k spacer and said upper surface of said fin.

3 . The semiconductor device of claim 1 , wherein a thickness of said non-ferroelectric high-k material layer is less than a thickness of said ferroelectric high-k spacer.

4 . The semiconductor device of claim 1 , further comprising a cap layer positioned between said ferroelectric high-k spacer and said non-ferroelectric high-k material layer.

5 . The semiconductor device of claim 4 , wherein said cap layer is positioned on and in direct contact with said ferroelectric high-k spacer.

6 . The semiconductor device of claim 4 , wherein said cap layer comprises titanium nitride.

7 . The semiconductor device of claim 1 , wherein said ferroelectric high-k spacer comprises hafnium oxide.

8 . The semiconductor device of claim 1 , wherein said fin is a first fin positioned over a first region of said semiconductor substrate, the semiconductor device further comprising a second fin positioned over a second region of said semiconductor substrate, said non-ferroelectric high-k material layer continuously covering sidewall and upper surfaces of said second fin.

9 . The semiconductor device of claim 8 , wherein said non-ferroelectric high-k material layer is positioned on and in direct contact with at least one of said sidewall surfaces and said upper surface of said second fin.

10 . The semiconductor device of claim 8 , further comprising a silicon oxide material positioned between said second fin and said non-ferroelectric high-k material layer.

11 . The semiconductor device of claim 8 , wherein a height level, relative to an upper surface of said semiconductor substrate, of an upper surface of said portion of said non-ferroelectric high-k material layer that is positioned on and in direct contact with said upper surface of said first fin is substantially equal to a height level, relative to said upper surface of said semiconductor substrate, of a second portion of said non-ferroelectric high-k material layer covering said upper surface of said second fin.

12 . A semiconductor device, comprising:
a semiconductor substrate; a fin positioned above a device region of said semiconductor substrate, said fin comprising a semiconductor material; a ferroelectric high-k spacer positioned adjacent to sidewall surfaces of said fin; a cap layer positioned on and in direct contact with an outer surface of said ferroelectric high-k spacer; and a non-ferroelectric high-k material layer extending continuously over and covering said ferroelectric high-k spacer, said cap layer and said fin, wherein a portion of said non-ferroelectric high-k material layer is positioned on and in direct contact with said semiconductor material at an upper surface of said fin.

13 . The semiconductor device of claim 12 , wherein said ferroelectric high-k spacer comprises hafnium oxide.

14 . The semiconductor device of claim 12 , wherein said cap layer comprises titanium nitride.

15 . The semiconductor device of claim 12 , wherein said ferroelectric high-k spacer covers an entirety of said sidewall surfaces of said fin.

16 . A semiconductor device structure, comprising:
a semiconductor substrate; a first semiconductor device positioned over a first region of said semiconductor substrate, said first semiconductor device comprising:
a first fin;
a ferroelectric high-k spacer covering sidewall surfaces of said first fin;
a first non-ferroelectric high-k material layer covering said ferroelectric high-k spacer and an upper surface of said first fin; and
a cap layer positioned between said ferroelectric high-k spacer and said first non-ferroelectric high-k material layer; and
a second semiconductor device positioned over a second region of said semiconductor substrate, said second semiconductor device comprising:
a second fin; and
a second non-ferroelectric high-k material layer covering sidewall and upper surfaces of said second fin, wherein a first height level, relative to an upper surface of said semiconductor substrate, of an upper surface of a portion of said first non-ferroelectric high-k material layer that covers said upper surface of said first fin is substantially equal to a second height level, relative to said upper surface of said semiconductor substrate, of a portion of said second non-ferroelectric high-k material layer that covers said upper surface of said second fin.

17 . The semiconductor device structure of claim 16 , wherein said first semiconductor device represents a storage device and said second semiconductor device represents at least one of a logic device and an SRAM device of an integrated circuit structure.

18 . The semiconductor device structure of claim 16 , wherein said first and second non-ferroelectric high-k material layers each comprise a same high-k material.

19 . The semiconductor device structure of claim 16 , wherein said first non-ferroelectric high-k material layer is positioned on and in direct contact with said upper surface of said first fin.

20 . The semiconductor device structure of claim 16 , further comprising a silicon oxide material positioned between said first non-ferroelectric high-k material layer and said upper surface of said first fin and between said second non-ferroelectric high-k material layer and said upper surface of said second fin.

Assignees

• Globalfoundries Inc

Inventors

• Flachowsky Stefan
• Illgen Ralf
• Hoentschel Jan

Classifications

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title