Device and method for testing semiconductor devices

Patent metadata

Field	Value
Publication number	US-2022390502-A1
Application number	US-202217887529-A
Country	US
Kind code	A1
Filing date	Aug 15, 2022
Priority date	Aug 6, 2020
Publication date	Dec 8, 2022
Grant date	—

Abstract

A testing circuit includes a first circuit and a second circuit. The first circuit and second circuit have a first capacitor and a second capacitor. The first circuit is connected to a first transistor. The second circuit is connected to a second transistor. A first inductor has a first terminal connected to an input of the testing circuit and a second terminal connected to a source of the second transistor. A first diode has an anode connected to ground and a cathode connected to the second terminal of the first inductor. The second capacitor has a first terminal connected to a drain of the second transistor and a second terminal connected to ground. The first capacitor has a first terminal connected to the input of the testing circuit and a second terminal connected to ground.

First claim

What is claimed is:

1 . A testing circuit, comprising:
a first circuit having a first capacitor and a second capacitor, the first circuit configured to transfer at least a portion of a first voltage across the first capacitor to the second capacitor; and a second circuit having the first capacitor and the second capacitor, the second circuit configured to transfer at least a portion of a second voltage across the second capacitor to the first capacitor, wherein the first circuit is connected to a first transistor; the first transistor has a gate configured to receive a first pulse signal; the portion of the first voltage is transferred from the first capacitor to the second capacitor during a period of the first pulse signal; the second circuit is connected to a second transistor; the second transistor has a gate configured to receive a second pulse signal; and the portion of the second voltage is transferred from the second capacitor to the first capacitor during a period of the second pulse signal; wherein the second circuit further comprises:
a first inductor having a first terminal connected to an input of the testing circuit and a second terminal connected to a source of the second transistor; and
a first diode having an anode connected to ground and a cathode connected to the second terminal of the first inductor,
wherein the second capacitor has a first terminal connected to a drain of the second transistor and a second terminal connected to ground, and
wherein the first capacitor has a first terminal connected to the input of the testing circuit and a second terminal connected to ground.

2 . The testing circuit of claim 1 , wherein
the first pulse signal has a first duty cycle; the second pulse signal has a second duty cycle; and the first duty cycle is substantially equal to 1 minus the second duty cycle.

3 . The testing circuit of claim 2 , wherein the first circuit further comprises:
a second inductor having a first terminal connected to an input of the testing circuit and a second terminal connected to a drain of the first transistor; and a second diode having an anode connected to the second terminal of the second inductor and a cathode connected to a first terminal of the second capacitor, wherein the second capacitor has a second terminal connected to ground, wherein the first capacitor has a first terminal connected to the input of the testing circuit and a second terminal connected to ground, and wherein the first transistor has a source connected to ground.

4 . The testing circuit of claim 3 , wherein
in the cast that the first transistor is turned on, the first capacitor is configured to release energy to the second inductor to increase a first current of the second inductor; and in the case that the first transistor is turned off, the second inductor is configured to charge the second capacitor to increase the second voltage of the second capacitor.

5 . The testing circuit of claim 4 , wherein
in the case that the first transistor is turned on, the first current flows from the second inductor through the first transistor to ground; and in the case that the first transistor is turned off, the first current flows from the second inductor through the second diode to the second capacitor.

6 . The testing circuit of claim 1 , wherein the second circuit is configured to perform at least one of: a buck circuit test, an aging test and a SSOA test for the second transistor.

7 . The testing circuit of claim 1 , wherein
the gate of the first transistor is connected to a pulse width modulation (PWM) controller and configured to receive the first pulse signal from the PWM controller; and the gate of the second transistor is connected to the PWM controller and configured to receive the second pulse signal from the PWM controller.

8 . The testing circuit of claim 1 , wherein
in the cast that the second transistor is turned on, the second capacitor is configured to release energy to the first inductor to increase a second current of the first inductor; and in the case that the second transistor is turned off, the first inductor is configured to charge the first capacitor to increase the first voltage of the first capacitor.

9 . The testing circuit of claim 8 , wherein
in the case that the second transistor is turned on, the second current flows from the second capacitor through the second transistor to the first inductor; and in the case that the second transistor is turned off, the second current flows from the first diode through the first inductor to the first capacitor.

10 . The testing circuit of claim 9 , wherein the first circuit is configured to perform at least one of: a boost circuit test, an aging test and a switching safe operating area (SSOA) test for the first transistor.

11 . The testing circuit of claim 1 , wherein the first transistor and the second transistor include group III nitride transistors.

12 . The testing circuit of claim 1 , further comprising a third diode connected between an input of the testing circuit and the second capacitor.

13 . A testing circuit, comprising:
a first circuit having a first capacitor and a second capacitor, the first circuit configured to transfer at least a portion of a first voltage across the first capacitor to the second capacitor, wherein the first circuit is connected to a first transistor; and a second circuit having the first capacitor and the second capacitor, the second circuit configured to transfer at least a portion of a second voltage across the second capacitor to the first capacitor, wherein the second circuit is connected to a second transistor and wherein the second circuit further comprises:
a first inductor having a first terminal connected to an input of the testing circuit and a second terminal connected to a source of the second transistor; and
a first diode having an anode connected to ground and a cathode connected to the second terminal of the first inductor,
wherein the second capacitor has a first terminal connected to a drain of the second transistor and a second terminal connected to ground, and
wherein the first capacitor has a first terminal connected to the input of the testing circuit and a second terminal connected to ground.

14 . The testing circuit of claim 13 , wherein
in the cast that the second transistor is turned on, the second capacitor is configured to release energy to the first inductor to increase a second current of the first inductor; and in the case that the second transistor is turned off, the first inductor is configured to charge the first capacitor to increase the first voltage of the first capacitor.

15 . The testing circuit of claim 14 , wherein
in the case that the second transistor is turned on, the second current flows from the second capacitor through the second transistor to the first inductor; and in the case that the second transistor is turned off, the second current flows from the first diode through the first inductor to the first capacitor.

16 . The testing circuit of claim 13 , wherein the first transistor and the second transistor include group III nitride transistors.

17 . A testing circuit, comprising:
a first circuit having a first capacitor and a second capacitor, the first circuit configured to transfer at least a portion of a first voltage across the first capacitor to the second capacitor, wherein the first circuit is connected to a first transistor to be tested; a second circuit having the first capacitor and the second capacitor, the second circu

Assignees

• Innoscience Zhuhai Technology Co Ltd

Inventors

• Li Jihua
• Zhang Tao
• Lin Wenjie

Classifications

• G01R31/2621

  for testing field effect transistors, i.e. FET's · CPC title

• G01R31/2607

  Circuits therefor (G01R31/2642 takes precedence) · CPC title

• G01R31/2894

  Aspects of quality control [QC] (G01R31/31718 takes precedence; program control for QC G05B19/41875) · CPC title

• G01R31/2601 Primary

  Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence) · CPC title

• G01R31/2623 Primary

  for measuring break-down voltage therefor · CPC title