Fully Aligned Subtractive Processes And Electronic Devices Therefrom

Patent metadata

Field	Value
Publication number	US-2022328352-A1
Application number	US-202217843966-A
Country	US
Kind code	A1
Filing date	Jun 18, 2022
Priority date	May 1, 2019
Publication date	Oct 13, 2022
Grant date	—

Abstract

Methods of forming fully aligned vias connecting two metal lines extending in two directions are described. The fully aligned via is aligned with the first metal line and the second metal line along both directions. A third metal layer is patterned on a top of a second metal layer in electrical contact with a first metal layer. The patterned third metal layer is misaligned from the top of the second metal layer. The second metal layer is recessed to expose sides of the second metal layer and remove portions not aligned sides of the third metal layer.

First claim

What is claimed is:

1 . A method of forming fully aligned vias, the method comprising:
forming a patterned fourth metal layer and patterned fourth etch stop layer on a third metal layer using a hard mask layer and a patterned photoresist; forming a patterned third metal layer on top of a patterned metal liner on a second metal layer using the patterned fourth metal layer and patterned fourth etch stop layer as a mask, the second metal layer in electrical contact with a first metal layer, the patterned third metal layer and patterned metal liner misaligned from the second metal layer so that a portion of the top of the second metal layer is exposed through the openings in the patterned third metal layer and the patterned metal liner; and recessing the second metal layer through the openings in the patterned third metal layer and patterned metal liner to lower the top of the second metal layer and expose sides of the second metal layer aligned with sides of the patterned third metal layer and a top surface of the second metal layer spaced a distance from a bottom surface of the metal liner, the top surface of the second metal layer spaced a distance in the range of about 5 A to about 100 A from the bottom surface of the metal liner.

2 . The method of claim 1 , further comprising depositing a dielectric layer on the recessed top of the second metal layer, the patterned metal line and the patterned third metal layer.

3 . The method of claim 2 , wherein the dielectric layer comprises a high-k dielectric material.

4 . The method of claim 3 , wherein the high-k dielectric material is deposited by a flowable chemical vapor deposition process.

5 . The method of claim 1 , wherein contact between the second metal layer and the third metal layer has an effective resistivity of less than or equal to about 20 μΩ-cm.

6 . The method of claim 1 , wherein contact between the second metal layer and the third metal layer has an Electron Mean Free Path less than or equal to about 20 nm.

7 . The method of claim 1 , wherein the second metal layer comprises one or more of ruthenium, molybdenum or tungsten.

8 . The method of claim 1 , wherein the fourth etch stop layer comprises one or more of titanium nitride, tantalum or tantalum nitride.

Assignees

• Applied Materials Inc

Inventors

• Ren He
• Jiang Hao
• Naik Mehul

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P50/266

  by vapour etching only · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title