Novel semiconductor device and structure

Patent metadata

Field	Value
Publication number	US-2016141274-A1
Application number	US-201615008444-A
Country	US
Kind code	A1
Filing date	Jan 28, 2016
Priority date	Dec 22, 2012
Publication date	May 19, 2016
Grant date	—

Abstract

An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a first wire structure constructed to provide power to a portion of the first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and a second wire structure constructed to provide power to a portion of the second transistors, where the second wire structure is isolated from the first wire structure to provide a different power voltage to the portion of the second transistors.

First claim

We claim:

1 . An Integrated Circuit device, comprising:
a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors; at least one metal layer providing interconnection between said plurality of first transistors;
a first wire structure constructed to provide power to a portion of said first transistors;
a second layer of less than 2 micron thickness, said second layer comprising a plurality of second single crystal transistors, said second layer overlying said at least one metal layer; and

a second wire structure constructed to provide power to a portion of said second transistors,
wherein said second wire structure is isolated from said first wire structure to provide a different power voltage to said portion of said second transistors.

2 . An Integrated Circuit device according to claim 1 , further comprising:
at least one conductive structure underneath at least one of said second single crystal transistors, said at least one conductive structure is constructed to provide a back-bias to at least one of said second single crystal transistors

3 . An Integrated Circuit device according to claim 1 , further comprising:
at least one thermal conduction path from at least one of said second single crystal transistors to an external surface of said Integrated Circuit device.

4 . An Integrated Circuit device according to claim 1 , further comprising:
a heat-spreader layer disposed between said first layer and said second layer.

5 . An Integrated Circuit device according to claim 1 ,
wherein at least a portion of said second wire structure is controlled by at least one of said transistors.

6 . An Integrated Circuit device according to claim 1 , further comprising:
a conductive layer disposed underneath said second layer,
wherein said conductive layer provides power to at least one of said second single crystal transistors.

7 . An Integrated Circuit device according to claim 1 , further comprising:
a conductive pad overlying at least one of said second single crystal transistors.

8 . An Integrated Circuit device, comprising:
a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors; at least one metal layer providing interconnection between said plurality of first transistors; a second layer of less than 2 micron thickness, said second layer comprising a plurality of second transistors, said second layer overlying said at least one metal layer; and at least one conductive structure constructed to provide power to a portion of said second transistors,
wherein said provide power is controlled by at least one of said transistors.

9 . An Integrated Circuit device according to claim 8 ,
wherein at least one of said second transistors comprises a back-bias structure.

10 . An Integrated Circuit device according to claim 8 , further comprising:
at least one thermal conduction path from at least one of said second transistors to an external surface of said Integrated Circuit device.

11 . An Integrated Circuit device according to claim 8 , further comprising:
a shielding layer,
wherein said shielding layer provides shielding for said at least one metal layer from heat resulting from optical annealing of said second transistors.

12 . An Integrated Circuit device according to claim 8 ,
wherein said at least one conductive structure is disposed between said base wafer and said second layer.

13 . An Integrated Circuit device according to claim 8 , further comprising:
a conductive pad overlying at least one of said second transistors.

14 . An Integrated Circuit device according to claim 8 , further comprising:
at least one thermal conduction path from said at least one conductive structure to an external surface of said Integrated Circuit device

15 . An Integrated Circuit device, comprising:
a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors; at least one metal layer providing interconnection between said plurality of first transistors; a second layer of less than 2 micron thickness, said second layer comprising a plurality of second transistors, said second layer overlying said at least one metal layer,
wherein said plurality of second transistors comprise single crystal;
a plurality of conductive pads,
wherein at least one of said conductive pads overlays at least one of said second transistors; and
at least one I/O circuit,
wherein said at least one I/O circuit is adapted to interface with external devices through at least one of said plurality of conductive pads.

16 . An Integrated Circuit device according to claim 15 ,
wherein at least one of said second transistors comprise a back-bias structure.

17 . An Integrated Circuit device according to claim 15 , further comprising:
at least one thermal conduction path from at least one of said second transistors to an external surface of said Integrated Circuit device.

18 . An Integrated Circuit device according to claim 15 , further comprising:
a shielding layer,
wherein said shielding layer provides shielding for said at least one metal layer from heat resulting from optical annealing of said second transistors.

19 . An Integrated Circuit device according to claim 15 , further comprising:
at least one heat spreader layer underneath said second layer.

20 . An Integrated Circuit device according to claim 15 , further comprising:
at least one conductive structure,
wherein said at least one conductive provides power to a portion of said second transistors,
wherein said provide power is controlled by at least one of said transistors.

Assignees

• Monolithic 3D Inc

Inventors

• Or-Bach Zvi
• Cronquist Brian

Classifications

• H10W90/752

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W72/01

  Manufacture or treatment · CPC title

• H10W42/271

  the arrangements being between stacked chips · CPC title