Semiconductor memory device and method for fabricating the semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2022254805-A1
Application number	US-202117362624-A
Country	US
Kind code	A1
Filing date	Jun 29, 2021
Priority date	Feb 9, 2021
Publication date	Aug 11, 2022
Grant date	—

Abstract

A semiconductor memory device may include a core pillar extended in a vertical direction, a channel layer having a first region covering a portion of a side surface of the core pillar and a second region covering the other portion of the side surface of the core pillar and a bottom surface of the core pillar, the second region abutting the first region, and a channel passivation layer formed in the first region of the channel layer and abutting the core pillar.

First claim

1 . A semiconductor memory device comprising:
a core pillar extended in a vertical direction; a channel layer having a first region covering a portion of a side surface of the core pillar and a second region covering an other portion of the side surface of the core pillar and a bottom surface of the core pillar, the second region abutting the first region; and a channel passivation layer formed in the first region of the channel layer and abutting the core pillar.

2 . The semiconductor memory device according to claim 1 , wherein the channel layer of the first region has a smaller thickness than the channel layer of the second region.

3 . The semiconductor memory device according to claim 1 , wherein the core pillar has substantially a trapezoid-type cross-sectional shape.

4 . The semiconductor memory device according to claim 1 , wherein the channel layer has substantially a cylinder shape, the channel layer of the first region has substantially a pipe shape, and the channel layer of the second region has substantially a cylinder shape.

5 . The semiconductor memory device according to claim 1 , wherein the channel layer includes a polycrystalline silicon layer, the channel passivation layer includes a silicon oxide layer formed by oxidizing the channel layer, and the core pillar includes a dielectric material.

6 . A semiconductor memory device comprising:
a gate stack formed on a source layer, and having a plurality of interlayer dielectric layers and gate conductive layers which are alternately stacked therein; and a plurality of channel structures formed through the gate stack, and each having a lower end extended into the source layer, wherein each of the channel structures comprises: a channel layer having a first region formed in the gate stack and a second region formed in the source layer so as to abut the first region; and a channel passivation layer formed in the first region of the channel layer.

7 . The semiconductor memory device according to claim 6 , wherein each of the channel structures further comprises:
a core pillar extended in a vertical direction; a capping layer formed over the core pillar; and a memory layer covering the channel layer, and abutting the gate stack and the source layer.

8 . The semiconductor memory device according to claim 7 , wherein the first region of the channel layer covers a portion of a side surface of the core pillar, and the second region of the channel layer covers the other portion of the side surface of the core pillar and a bottom surface of the core pillar.

9 . The semiconductor memory device according to claim 7 , wherein the channel layer covers a side surface of the capping layer, and is electrically coupled to the capping layer.

10 . The semiconductor memory device according to claim 7 , wherein the channel passivation layer is inserted between the channel layer and the core pillar, and has one end abutting the bottom surface of the capping layer.

11 . The semiconductor memory device according to claim wherein the memory layer comprises a stacked layer in which a blocking layer, a charge trap layer and a tunnel dielectric layer are sequentially stacked.

12 . The semiconductor memory device according to claim 6 , wherein the sum of the thickness of the channel layer of the first region and the thickness of the channel passivation layer is substantially equal to or larger than the thickness of the channel layer of the second region.

13 . The semiconductor memory device according to claim 6 , wherein each of the channel structures has a substantially trapezoid-type cross-sectional shape.

14 . The semiconductor memory device according to claim 6 , wherein the channel layer has a substantially cylinder shape, the channel layer of the first region has a substantially pipe shape, and the channel layer of the second region has a substantially cylinder shape.

15 . The semiconductor memory device according to claim 6 , wherein the channel layer includes a polycrystalline silicon layer, and the channel passivation layer includes a silicon oxide layer formed by oxidizing the channel layer.

16 . The semiconductor memory device according to claim 6 , wherein the source layer comprises a stacked layer having a plurality of conductive layers stacked therein, and any one of the plurality of conductive layers is electrically coupled to the channel layer.

17 - 30 . (canceled)

Assignees

• Sk Hynix Inc

Inventors

• Lee Yu Jeong
• Yun dae hwan
• Choi Gil Bok

Classifications

• H10P14/69215 Primary

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6309

  of silicon in uncombined form, i.e. pure silicon · CPC title

• H10P14/3802

  Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth · CPC title

• H10P14/3454

  Amorphous · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title