Semiconductor component including a dielectric layer

Patent metadata

Field	Value
Publication number	US-2022238791-A1
Application number	US-202017614706-A
Country	US
Kind code	A1
Filing date	Jun 23, 2020
Priority date	Jul 5, 2019
Publication date	Jul 28, 2022
Grant date	—

Abstract

A semiconductor component that includes at least one dielectric layer and at least one first electrode and one second electrode. A first defect type and a second defect type, which is different from the first defect type, are also present in dielectric layer. The at least two different defect types accumulate at one of the two electrodes as a function of a main operating voltage applied between the first electrode and the second electrode, and of a main operating temperature that is present at characteristic times τ1 and τ2, and generate the maximum changes in barrier height δΦ1 and δΦ2 at the electrodes. τ1 and δΦ1 are associated with the first defect type, and τ2 and δΦ2 are associated with the second defect type. τ1<τ2 and δΦ1<δΦ2 apply.

First claim

1 - 7 . (canceled)

8 . A semiconductor component, comprising:
at least one dielectric layer; and at least one first electrode and at least one second electrode, wherein at least one first defect type and at least one second defect type, which is different from the first defect type, are present in the dielectric layer, the at least one first defect type and the at least one second defect type accumulating at one of the first and second electrodes, as a function of a main operating voltage applied between the first electrode and the second electrode, and a main operating temperature that is present at characteristic times τ 1 and τ 2 , and generating maximum changes in barrier height δΦ 1 and δΦ 2 at the first and second electrodes, τ 1 and δΦ 1 being associated with the first defect type, and τ 2 and δΦ 2 being associated with the second defect type, where τ 1 <τ 2 and δΦ 1 <δΦ 2 apply.

9 . The semiconductor component as recited in claim 8 , wherein at least one further, third defect type is present in the dielectric layer, the third defect type accumulating at one of the first and second electrodes as a function of the main operating voltage applied between the first electrode and the second electrode, and of the main operating temperature that is present, at a characteristic time τ 3 , and generating a maximum change in barrier height δΦ 3 at the first and second electrodes, where τ 1 <τ 2 <τ 3 applies, a sequence of the change in barrier height differing from a sequence δΦ 1 >δΦ 2 >δΦ 3 .

10 . The semiconductor component as recited in claim 8 , wherein the dielectric layer is a polycrystalline oxidic high-k dielectric.

11 . The semiconductor component as recited in claim 10 , wherein the dielectric layer is a PZT layer or a KNN layer.

12 . The semiconductor component as, recited in claim 8 , wherein the dielectric layer is a sputtered PZT layer.

13 . The semiconductor component as recited in claim 12 , wherein the sputtered PZT layer has a PZT deposition temperature of less than 500° C.

14 . The semiconductor component as recited in claim 12 , wherein the sputtered PZT layer has a composition of Pb x (Zr 0.52 Ti 0.48 )O 3 , where 1.2≤x≤1.3.

15 . The semiconductor component as recited in claim 12 , wherein the sputtered PZT layer has a nickel content between 0.1 and 1 atom percent.

Assignees

• Bosch Gmbh Robert

Inventors

• Monteiro Diniz Reis Daniel
• Pantel Daniel
• Schatz Frank
• Tomaschko Jochen
• Mews Mathias
• Schary Timo

Classifications

• H01L41/316

  Electricity · mapped topic

• H01L41/0805

  Electricity · mapped topic

• H01L41/1876 Primary

  Electricity · mapped topic

• H10N30/704 Primary

  based on piezoelectric or electrostrictive films or coatings · CPC title

• H10N30/076

  by vapour phase deposition · CPC title