Vertical non-volatile memory device including thermoelectric device, semiconductor package including the memory device, and heat dissipation method of the memory device

Patent metadata

Field	Value
Publication number	US-2022238541-A1
Application number	US-202117487317-A
Country	US
Kind code	A1
Filing date	Sep 28, 2021
Priority date	Jan 27, 2021
Publication date	Jul 28, 2022
Grant date	—

Abstract

A vertical non-volatile memory device capable of stably maintaining an operating temperature in a chip level, a semiconductor package including the memory device, and a heat dissipation method of the memory device. The vertical non-volatile memory device includes a substrate on which a cell array area and an extension area are defined, a vertical channel structure formed on the substrate, a thermoelectric device including at least two semiconductor pillars formed on the substrate, and a stacked structure on the substrate. The stacked structure includes a gate electrode layer and an interlayer insulation layer which are stacked alternately along sidewalls of the vertical channel structure and the at least two semiconductor pillars. The at least two semiconductor pillars include an n-type semiconductor pillar and a p-type semiconductor pillar which are electrically connected to each other through a conductive layer on the substrate.

First claim

1 . A vertical non-volatile memory device comprising:
a substrate on which a cell array area and an extension area are defined, the extension area including an electrode pad extending from the cell array area in a first direction; a vertical channel structure formed on the substrate to extend perpendicular to a top surface of the substrate; a thermoelectric device on the substrate, the thermoelectric device comprising at least two semiconductor pillars extending perpendicular to the top surface of the substrate; and a stacked structure on the substrate, the stacked structure comprising a gate electrode layer and an interlayer insulation layer which are stacked alternately along sidewalls of the vertical channel structure and the at least two semiconductor pillars, wherein the at least two semiconductor pillars comprise an n-type semiconductor pillar and a p-type semiconductor pillar which are electrically connected to each other through a conductive layer on the substrate.

2 . The vertical non-volatile memory device of claim 1 , wherein each of the n-type semiconductor pillar and the p-type semiconductor pillar is connected, through a lower end thereof, to the conductive layer, and
when the thermoelectric device is turned on, the n-type semiconductor pillar is connected to a power source through a top end thereof, the p-type semiconductor pillar is connected to ground through a top end thereof, and heat from the substrate is dissipated through the at least two semiconductor pillars.

3 . The vertical non-volatile memory device of claim 1 , wherein the at least two semiconductor pillars comprise a plurality of n-type semiconductor pillars and a plurality of p-type semiconductor pillars which are arranged in a second direction perpendicular to the first direction, and
the plurality of n-type semiconductor pillars and the plurality of p-type semiconductor pillars are arranged collectively for the same conductive type in the second direction or are arranged alternately in the second direction.

4 . The vertical non-volatile memory device of claim 3 , wherein the plurality of n-type semiconductor pillars are connected, through a top end thereof, in common to a first line and the first line is connected to a first chip pad connected to a power source, and
the plurality of p-type semiconductor pillars are connected, through a top end thereof, in common to a second line and the second line is connected to a second chip pad connected to ground.

5 . The vertical non-volatile memory device of claim 1 , wherein each of the at least two semiconductor pillars has a cylindrical shape and a side surface thereof is surrounded by a pillar insulation layer.

6 . The vertical non-volatile memory device of claim 1 , wherein a common source line (CSL) is arranged on the substrate, and
each of the n-type semiconductor pillar and the p-type semiconductor pillar contacts, through a lower end thereof, the common source line.

7 . The vertical non-volatile memory device of claim 1 , wherein, when the n-type semiconductor pillar is connected, through a top end thereof, to a power source and the p-type semiconductor pillar is connected, through a top end thereof, to ground, carriers of the n-type semiconductor pillar move to the power source and carriers of the p-type semiconductor pillar move to the ground, and
heat generated in the substrate and the stacked structure is dissipated by moving to the power source and the ground by the carriers.

8 . The vertical non-volatile memory device of claim 1 , wherein at least one temperature sensor based on a diode is arranged in the cell array area, and
a temperature in the substrate and the stacked structure is measured using the at least one temperature sensor.

9 . The vertical non-volatile memory device of claim 8 , wherein, when the temperature measured using the at least one temperature sensor exceeds a set reference temperature, the thermoelectric device is turned on and operates.

10 . A vertical non-volatile memory device comprising:
a substrate on which a cell array area and an extension area are defined, the extension area includes an electrode pad extending from the cell array area in a first direction; a vertical channel structure formed on the substrate by extending perpendicular to a top surface of the substrate; a thermoelectric device on the substrate, the thermoelectric device comprising at least two semiconductor pillars extending perpendicular to the top surface of the substrate; a stacked structure on the substrate, the stacked structure comprising a gate electrode layer and an interlayer insulation layer which are stacked alternately along sidewalls of the vertical channel structure and the at least two semiconductor pillars; and at least one temperature sensor arranged in the cell array area, on the substrate, wherein the at least two semiconductor pillars comprise an n-type semiconductor pillar and a p-type semiconductor pillar which are electrically connected to each other through a conductive layer on the substrate, and when a temperature measured using the at least one temperature sensor exceeds a set reference temperature, the n-type semiconductor pillar is connected, through a top end thereof, to a power source and the p-type semiconductor pillar is connected through a top end thereof, to ground, such that the thermoelectric device is turned on and heat from the substrate is dissipated through the at least two semiconductor pillars.

11 . The vertical non-volatile memory device of claim 10 , wherein the at least two semiconductor pillars comprise a plurality of n-type semiconductor pillars and a plurality of p-type semiconductor pillars which are arranged in a second direction perpendicular to the first direction, and
the plurality of n-type semiconductor pillars and the plurality of p-type semiconductor pillars are arranged collectively for the same conductive type in the second direction or are arranged alternately in the second direction, and the plurality of n-type semiconductor pillars are connected to a first chip pad connected to the power source, through a first line, and the plurality of p-type semiconductor pillars are connected to a second chip pad connected to the ground, through a second line.

12 . The vertical non-volatile memory device of claim 10 , wherein the at least one temperature sensor is based on a diode and measures a temperature in the substrate and the stacked structure.

13 . A semiconductor package comprising:
a package substrate; at least one semiconductor chip mounted on the package substrate; a connection line electrically connecting the at least one semiconductor chip to the package substrate; and a sealant sealing the at least one semiconductor chip and the connection line, wherein the at least one semiconductor chip comprises a vertical non-volatile memory device comprising a semiconductor substrate, a vertical channel structure, a thermoelectric device, and a stacked structure, the thermoelectric device comprises at least two semiconductor pillars including an n-type semiconductor pillar and a p-type semiconductor pillar on the semiconductor substrate and extending through the stacked structure perpendicularly to a top surface of the semiconductor substrate, and the n-type semiconductor pillar and the p-type semiconductor pillar are electrically connected to each other through a conductive layer on the semiconductor substrate.

14 . The semiconductor package of claim 13 , wherein a cell array area and an extension area are defined on the semiconductor substrate, the extension area includes an electrode pad extending from the

Assignees

• Samsung Electronics Co Ltd

Inventors

• Byun Jaebeom
• Kim Jongsam
• Park Sehwan

Classifications

• H10W40/28 Primary

  comprising Peltier coolers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/656

  Fan-in layouts · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title