Integrated thermoelectric cooler for three-dimensional stacked dram and temperature-inverted cores

Patent metadata

Field	Value
Publication number	US-2018358080-A1
Application number	US-201715618349-A
Country	US
Kind code	A1
Filing date	Jun 9, 2017
Priority date	Jun 9, 2017
Publication date	Dec 13, 2018
Grant date	—

Abstract

Managing temperature of a semiconductor device having a temperature inverted processor core and stacked memory by operation of an integrated thermoelectric cooler. The thermoelectric cooler is operated to pump heat from a stacked memory device that requires a cool operating temperature to a temperature inverted processor core that maintains a higher operating temperature until threshold operating temperatures are achieved.

First claim

What is claimed is:

1 . A method of thermal management, comprising:
determining a first operating temperature threshold for a first circuit and a second operating temperature threshold for a second circuit, the second circuit being a temperature inverted circuit coupled to the first circuit; and responsive to a temperature of the second circuit being less than the second operating temperature threshold, transferring heat by operating a thermoelectric cooler, from the first circuit to the second circuit, wherein the first operating temperature threshold is lower than the second operating temperature threshold.

2 . The method of claim 1 , wherein operating the thermoelectric cooler comprises monitoring a temperature of the first circuit by one or more sensors associated with the first circuit and monitoring the temperature of the second circuit by one or more sensors associated with the second circuit.

3 . The method of claim 1 , wherein transferring heat is based on a temperature inversion that causes the second circuit to increase speed and frequency as temperature increases.

4 . The method of claim 2 , wherein the first circuit comprises a three-dimensional stacked memory circuit.

5 . The method of claim 4 , wherein the second circuit comprises logic layers of a processor.

6 . The method of claim 4 , wherein monitoring the temperature of the second circuit comprises: in response to detecting that the logic layers are overheating, reducing a number of operating thermoelectric coolers.

7 . The method of claim 4 , wherein monitoring the temperature of the second circuit comprises: in response to detecting that the logic layers are overheating, reducing an operating voltage and frequency of the logic layers.

8 . A semiconductor device, comprising:
a three-dimensional (3D) stacked memory; one or more logic core layers that are temperature-inverted coupled to the three-dimensional stacked memory; and a thermoelectric cooler coupled between the three-dimensional stacked memory and the one or more logic core layers, wherein the thermoelectric cooler is configured to pump heat from the three-dimensional stacked memory to the one or more logic core layers.

9 . The semiconductor device of claim 8 , further comprising one or more thermal sensors integrated within the 3D stacked memory and the one or more logic layers.

10 . The semiconductor device of claim 8 , wherein the 3D stacked memory operates at a first temperature, the one or more logic core layers operates at a second temperature, and the first temperature is cooler than the second temperature.

11 . A semiconductor device, comprising:
one or more logic core layers; a plurality of memory layers stacked together and coupled to the one or more logic core layers that are temperature-inverted; and a thermoelectric cooler integrated between the one or more core layers and the plurality of memory layers, wherein the thermoelectric cooler is configured to pump heat from the plurality of memory layers to the one or more logic core layers, wherein the plurality of memory layers maintains a constant cool temperature.

12 . The semiconductor device of claim 11 , wherein a first surface of the thermoelectric cooler couples to a cold junction and a second surface of the thermoelectric cooler couples to a hot junction.

13 . The semiconductor device of 12 , wherein the cold junction comprises the plurality of memory layers and the hot junction comprises the one or more core layers.

14 . The semiconductor device of claim 11 , further comprising:
a first thermal sensor situated within the one or more core layers; and a second thermal sensor situated within the plurality of memory layers.

15 . The semiconductor device of claim 14 , further comprising:
a temperature aware controller operative to monitor the first thermal sensor and the second thermal sensor.

16 . The semiconductor device of claim 15 , wherein the temperature aware controller is further operative to execute a runtime thermal management scheme that controls the first thermal sensor and the second thermal sensor.

17 . The semiconductor device of claim 11 , wherein the plurality of memory layers is a three-dimensional stacked memory.

18 . The semiconductor device of claim 17 , wherein the three-dimensional stacked memory is a dynamic random-access memory (DRAM).

19 . The semiconductor device of 17 , wherein the three-dimensional stacked memory is a high bandwidth memory.

20 . The semiconductor device of claim 11 , wherein the 3D stacked memory and the one or more logic core layers are associated with a multi-chip module.

Assignees

• Advanced Micro Devices Inc

Inventors

• Huang Wei

Classifications

• H10W40/28

  comprising Peltier coolers · CPC title

• G11C7/04 Primary

  with means for avoiding disturbances due to temperature effects · CPC title

• H01L23/38

  Electricity · mapped topic

• G11C11/4078 Primary

  Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells (protection of memory contents during checking or testing G11C29/52) · CPC title

• H01L27/16

  Electricity · mapped topic