Square-gate source-follower for cmos image sensor pixel

Patent metadata

Field	Value
Publication number	US-2022216252-A1
Application number	US-202117141141-A
Country	US
Kind code	A1
Filing date	Jan 4, 2021
Priority date	Jan 4, 2021
Publication date	Jul 7, 2022
Grant date	—

Abstract

Techniques are described for implementing a square-gate source-follower (SGSF) transistor for integration with complementary metal-oxide semiconductor (CMOS) image sensor (CIS) pixels. The SGSF transistor can have an active layer with active regions, including a drain region separated from each of two source regions to form parallel current channels. A square-gate structure layer includes main-gate regions, each disposed above a corresponding one of the current channels, and a side-gate region to couple the main-gate regions. At a particular physical width (W) and current channel length (L), the parallel current channels can act similarly to a conventional linear source-follower having dimensions of 2W and the same L. SGSF implementations can provide a number of features, including higher frame rate, lower power consumption, and lower noise, as compared to those of a conventional source-follower transistor of comparable W and L dimensions.

First claim

What is claimed is:

1 . A source-follower transistor comprising:
an active layer comprising a drain-doped region separated from a first source-doped region by a first current channel, and separated from a second source-doped region by a second current channel; and a square-gate layer comprising:
a first main-gate region disposed above the first current channel to a first side of the drain-doped region;
a second main-gate region disposed above the second current channel to a second side of the drain-doped region opposite the first side of the drain-doped region; and
a side-gate region disposed to a third side of the drain-doped region to electrically couple the first main-gate region to the second main-gate region.

2 . The source-follower transistor of claim 1 , further comprising:
an edge-isolation region running along a first edge of the source-follower transistor corresponding to the third side of the drain region, such that the side-gate region at least partially overlaps the edge-isolation region.

3 . The source-follower transistor of claim 2 , wherein the edge-isolation region is a shallow trench isolation (STI) region.

4 . The source-follower transistor of claim 1 , wherein the side-gate region is a first side-gate region, and further comprising:
a second side-gate region disposed to a fourth side of the drain region opposite the third side of the drain region to further electrically couple the first main-gate region to the second main-gate region.

5 . The source-follower transistor of claim 4 , further comprising:
a first edge-isolation region running along a first edge of the source-follower transistor that corresponds to the third side of the drain region, such that the first side-gate region at least partially overlaps the first edge-isolation region; and a second edge-isolation region running along a second edge of the source-follower transistor that corresponds to the fourth side of the drain region, such that the second side-gate region at least partially overlaps the second edge-isolation region.

6 . The source-follower transistor of claim 1 , further comprising:
a drain contact physically and electrically coupled with the drain-doped region; a first source contact physically and electrically coupled with the first source-doped region; a second source contact physically and electrically coupled with the second source-doped region; and a gate contact physically and electrically coupled with the first main-gate region, and electrically coupled with the second main-gate region via the side-gate region.

7 . The source-follower transistor of claim 1 , wherein the first current channel and the second current channel each has a same nominal channel length.

8 . The source-follower transistor of claim 1 , wherein:
the source-follower transistor has a width of W; and each of the first current channel and the second current channel has a nominal channel length (L); and
0.6 W≤L≤W.

9 . The source-follower transistor of claim 1 , wherein:
the active layer is a substrate structure; each of the drain-doped region, the first source-doped region, and the second source-doped region is a respective n-doped region of the substrate structure; each of the first and second current channels corresponds to respective p-doped region of the substrate structure; the square-gate layer is a polysilicon structure; and the first and second main-gate regions of the polysilicon structure are isolated from the first and second current channels by a thin silicon dioxide layer.

10 . A semiconductor image sensor comprising:
a pixel having:
a photodiode; and
a square-gate source-follower (SGSF) transistor comprising:
an active layer comprising a drain-doped region separated from a first source-doped region by a first current channel, and separated from a second source-doped region by a second current channel; and
a square-gate layer comprising a first main-gate region disposed above the first current channel to a first side of the drain-doped region, a second main-gate region disposed above the second current channel to a second side of the drain-doped region opposite the first side of the drain-doped region, and a side-gate region disposed to a third side of the drain-doped region to electrically couple the first main-gate region to the second main-gate region,
wherein the square-gate layer is coupled with the photodiode.

11 . The semiconductor image sensor of claim 10 , further comprising:
a select transistor to couple the pixel with a bus, wherein the first and second source-doped regions are coupled with the select transistor.

12 . The semiconductor image sensor of claim 10 , further comprising:
an array of instances of the pixel.

13 . The semiconductor image sensor of claim 10 , wherein each pixel comprises a plurality of photodiodes, all coupled with the square-gate layer.

14 . The semiconductor image sensor of claim 10 , wherein the SGSF transistor further comprises:
an edge-isolation region running along a first edge of the SGSF transistor that corresponds to the third side of the drain-doped region, such that the side-gate region at least partially overlaps the edge-isolation region.

15 . The semiconductor image sensor of claim 10 , wherein the side-gate region is a first side-gate region, and the SGSF transistor further comprises:
a second side-gate region disposed to a fourth side of the drain-doped region opposite the third side of the drain-doped region to further electrically couple the first main-gate region to the second main-gate region.

16 . The semiconductor image sensor of claim 15 , wherein the SGSF transistor further comprises:
a first edge-isolation region running along a first edge of the SGSF transistor that corresponds to the third side of the drain-doped region, such that the first side-gate region at least partially overlaps the first edge-isolation region; and a second edge-isolation region running along a second edge of the SGSF transistor that corresponds to the fourth side of the drain-doped region, such that the second side-gate region at least partially overlaps the second edge-isolation region.

17 . The semiconductor image sensor of claim 10 , wherein the SGSF transistor further comprises:
a drain contact physically and electrically coupled with the drain-doped region; a first source contact physically and electrically coupled with the first source-doped region; a second source contact physically and electrically coupled with the second source-doped region; and a gate contact physically and electrically coupled with the first main-gate region, and electrically coupled with the second main-gate region via the side-gate region.

18 . The semiconductor image sensor of claim 10 , wherein the first current channel and the second current channel each has a same nominal channel length.

Assignees

• Shenzhen Goodix Tech Co Ltd

Inventors

• Gao Yunfei
• Oh Tae Seok
• Xiao Jinwen

Classifications

• H04N25/76

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H10F39/80377

  characterised by the channel of the transistor, e.g. channel having a doping gradient · CPC title

• H10F39/802 Primary

  Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes · CPC title

• H10F39/18

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title

• H10F39/80373 Primary

  characterised by the gate of the transistor · CPC title