Gold through silicon mask plating

Patent metadata

Field	Value
Publication number	US-2022216104-A1
Application number	US-202017430617-A
Country	US
Kind code	A1
Filing date	Feb 13, 2020
Priority date	Feb 14, 2019
Publication date	Jul 7, 2022
Grant date	—

Abstract

Systems and methods are provided for method for etch assisted gold (Au) through silicon mask plating (EAG-TSM). An example method comprises providing a seed layer on a substrate and providing a silicon mask on at least a portion of the seed layer on the substrate. The silicon mask includes one or more via to be filled with Au. The masked substrate is subjected to at least one processing cycle, each processing cycle including an Au plating sub-step and an etch treatment sub-step. The cycles are repeated until a selected via fill thickness is achieved.

First claim

1 . A method for etch assisted gold (Au) through silicon mask plating (EAG-TSM), the method comprising:
providing a seed layer on a substrate; providing a silicon mask on at least a portion of the seed layer on the substrate, the silicon mask including one or more via to be filled with Au; subjecting the masked substrate to at least one processing cycle, each processing cycle including an Au plating sub-step and an etch treatment sub-step; and repeating the at least one processing cycle until a selected via fill thickness is achieved.

2 . The method of claim 1 , wherein residual Au deposited adjacent a via by the plating sub-step is removed by the etch treatment sub-step.

3 . The method of claim 2 , further comprising generating a via-fill efficiency based on a degree of via fill versus a degree of residual Au.

4 . The method of claim 3 , further comprising adjusting the via-fill efficiency based on an inclusion of Sulphur trioxide (SO 3 ) a chemistry of the Au plating solution in the plating sub-step.

5 . The method of claim 3 , further comprising adjusting the via-fill efficiency based on an inclusion of cyanide (CN) in a chemistry of the Au plating solution in the plating sub-step.

6 . The method of claim 1 , wherein an etchant in the etch treatment sub-step includes I-/I2 in a 6:1 molar ratio.

7 . The method of claim I, wherein an etchant in the etch treatment sub-step includes aqua-regia in a 1:3 molar ratio.

8 . The method of claim 1 , wherein a cycle time of a first cycle in the at least one cycle is equal to a cycle time of a second cycle in the at least one cycle.

9 . The method of claim 1 , wherein a cycle time of a first cycle in the at least one cycle is not equal to a cycle time of a second cycle in the at least one cycle.

10 . The method of claim 1 , wherein a frequency of applying the etch treatment sub-step during a first period of subjecting the masked substrate to the at least one processing cycle is different to a frequency of applying the etch treatment sub-step during a second period of subjecting the masked substrate to the at least one processing cycle.

11 . A plating system for a method of etch assisted gold Au) through silicon mask plating (EAG-TSM), the system comprising:
a cathode; an anode; an in-situ substrate processing module configured to perform alternating sub-steps of at least one processing cycle, the sub-steps including an Au plating sub-step and an etch treatment sub-step, the processing module common to each sub-step operation; a robot to receive or transfer a substrate to the processing module, the substrate including a seed layer and a silicon mask on at least a portion of the seed layer on the substrate, the silicon mask including one or more via to be filled with Au by the plating system; a substrate holder; and an etchant delivery means operable to deliver etchant during the etch treatment sub-step.

12 . The plating system of claim 11 , wherein the substrate holder is operable to lower the substrate into an Au plating solution in the processing module during the Au plating sub-step and withdraw the substrate from the plating solution after the Au plating sub-step.

13 , The plating system of claim 12 , wherein the substrate holder is further operable to hold the substrate in the path of an etchant during the etch treatment sub-step while the substrate holder is in the withdrawn position.

14 . The plating system of claim 12 , wherein the processing module is configured to repeat the at least one processing cycle until a selected via fill thickness is achieved.

15 . The plating system of claim 12 , wherein the substrate holder is configured to apply a selected substrate rotation speed during at least the etch treatment sub-step.

Assignees

• Lam Res Corp

Inventors

• Chua Lee Peng
• Liang Defu
• Blickensderfer Jacob Kurtis
• Ponnuswamy Thomas A
• Buckalew Bryan L
• Mayer Steven T

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/0595

  by using multiple deposition steps separated by etching steps · CPC title