Multi-level memory system power management apparatus and method

Patent metadata

Field	Value
Publication number	US-2022197519-A1
Application number	US-202017128072-A
Country	US
Kind code	A1
Filing date	Dec 19, 2020
Priority date	Dec 19, 2020
Publication date	Jun 23, 2022
Grant date	—

Abstract

A multi-level memory architecture scheme to dynamically balance a number of parameters such as power, thermals, cost, latency and performance for memory levels that are progressively further away from the processor in the platform based on how applications are using memory levels that are further away from processor cores. In some examples, the decision making for the state of the far memory (FM) is decentralized. For example, a processor power management unit (p-unit), near memory controller (NMC), and/or far memory host controller (FMHC) makes decisions about the power and/or performance state of the FM at their respective levels. These decisions are coordinated to provide the most optimum power and/or performance state of the FM for a given time. The power and/or performance state of the memories adaptively change to changing workloads and other parameters even when the processor(s) is in a particular power state.

First claim

What is claimed is:

1 . An apparatus comprising:
a plurality of processing cores; a first memory controller coupled to one or more first memory modules via a first link; a second memory controller coupled to one or more second memory modules via a second link; and a power management unit coupled to the plurality of processing cores, the first memory controller, and the second memory controller, wherein the power management unit is to determine power and/or performance policy and boundary conditions for the apparatus, and to communicate a power state for the first and/or second links via the first memory controller and/or the second memory controller.

2 . The apparatus of claim 1 , wherein the second memory controller manages power of the one or more second memory modules via the second link and based on a dynamic profile of workload fed to a memory device, wherein the memory device is coupled to the second memory modules and the second memory controller.

3 . The apparatus of claim 2 , wherein the memory device has precedence over the second memory controller and/or the power management unit to decide the power state of the second link.

4 . The apparatus of claim 1 , wherein the second memory controller includes a timer to determine exit latency from a power state of the second link, wherein the exit latency is considered by the second memory controller to determine a power state of the second link.

5 . The apparatus of claim 1 , wherein the power management unit receives memory access pattern hints for an operating system, and provides the memory access pattern hints to the second memory controller, wherein the second memory controller considers the memory access pattern hints to determine a power state of the second link.

6 . The apparatus of claim 1 , wherein the power and/or performance policy includes Hour of battery life, and quality of service.

7 . The apparatus of claim 1 , wherein the boundary conditions include power envelope, thermal limit, and maximum supply current.

8 . The apparatus of claim 1 , wherein the first link is a double data rate link, and wherein the first memory modules comprise dynamic random-access memory.

9 . The apparatus of claim 1 , wherein the second link is a peripheral component interface express link, wherein the second memory modules have slower exit latency than an exit latency of the first memory modules.

10 . The apparatus of claim 1 , wherein power state of the first and/or second links is decoupled from power states of the plurality of processing cores.

11 . A machine-readable storage media having machine-readable instructions that, when executed, cause one or more machines to perform a method comprising:
determining power and/or performance policy and boundary conditions for a processor system; communicating a first power state for a link via a memory controller; dynamically profiling workload feeding a memory device coupled to the memory controller; suggesting a second power state for the link based on the power and/or performance policy and boundary conditions and dynamically profiled workload.

12 . The machine-readable storage media of claim 11 , wherein the power and/or performance policy includes Hour of battery life, and quality of service.

13 . The machine-readable storage media of claim 11 , wherein the first power state for the link is same as the second power state for the link.

14 . The machine-readable storage media of claim 11 , wherein the first power state for the link is different as the second power state for the link.

15 . The machine-readable storage media of claim 11 , wherein the second power state takes precedence over the first power state.

16 . The machine-readable storage media of claim 11 , having machine-readable instructions that, when executed, cause the one or more machines to perform the method comprising:
determining exit latency from a power state of the second link; considering, by the memory controller, the exit latency to determine a power state of the second link.

17 . A system comprising:
far memory modules; near memory modules; a processor coupled to the far memory modules and the near memory modules; and a wireless device to allow the processor to communicate with another device, wherein the processor includes:
a plurality of processing cores;
a near memory controller coupled to the near memory modules via a first link;
a far memory controller coupled to the far memory modules via a second link; and
a power management unit coupled to the plurality of processing cores, the near memory controller, and the far memory controller, wherein the power management unit is to determine power and/or performance policy and boundary conditions for the processor, and to communicate a power state for the first and/or second links via the near memory controller and/or the far memory controller.

18 . The system of claim 17 , wherein the far memory controller manages power of the far memory modules via the second link and based on a dynamic profile of workload fed to a memory device, wherein the memory device is coupled to the far memory modules and the far memory controller.

19 . The system of claim 18 , wherein the memory device has precedence over the far memory controller and/or the power management unit to decide the power state of the second link.

20 . The system of claim 17 , wherein the far memory controller includes a timer to determine exit latency from a power state of the second link, wherein the exit latency is considered by the far memory controller to determine a power state of the second link.

Assignees

• Intel Corp

Inventors

• Kuo Chia-Hung
• Mukker Anoop
• Ooi Eng Hun
• Snir Avishay
• Venkatraman Shrinivas
• Tan Kuan Hua
• Lin Wai Ben

Classifications

• G06F13/4291

  using a clocked protocol · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F2213/0026

  PCI express · CPC title

• G06F2213/0042

  Universal serial bus [USB] · CPC title