Multilevel main memory indirection

Patent metadata

Field	Value
Publication number	US-2017160987-A1
Application number	US-201514961937-A
Country	US
Kind code	A1
Filing date	Dec 8, 2015
Priority date	Dec 8, 2015
Publication date	Jun 8, 2017
Grant date	—

Abstract

The present disclosure relates to a memory system with main memory. The main memory includes first level main memory and second level main memory. The first level main memory is configured to store indirection information providing reference to physical memory units of the second level main memory. Further, the memory system includes a memory controller configured to initiate an access of a physical memory unit of the second level main memory using the indirection information stored in the first level main memory.

First claim

What is claimed is:

1 . A memory controller configured to
access indirection information stored in a first level main memory, the indirection information providing a mapping between one or more logical addresses and one or more physical addresses of a second level main memory; and initiate an access of a physical memory address of the second level main memory using the indirection information stored in the first level main memory.

2 . The memory controller of claim 1 , further configured to
receive a request for access to a memory portion of the second level main memory, generate a logical address for the requested memory portion; and look up indirection information for the memory portion in the first level main memory using the generated logical address.

3 . The memory controller of claim 1 , further configured to
generate a memory request for the second level main memory using the indirection information of the first level main memory, the memory request including information on a physical address of the second level main memory, and transmit the memory request to the second level main memory.

4 . The memory controller of claim 1 , wherein the second level main memory is configured to modify, according to a wear leveling scheme, indirection information stored in the second level main memory, the indirection information providing a mapping between one or more logical addresses and one or more corresponding physical addresses of the second level main memory, and wherein the memory controller is further configured to
receive modified indirection information from the second level main memory, and update the indirection information of first level main memory based on the modified indirection information of the second level main memory.

5 . The memory controller of claim 1 , further configured to initiate a transfer of the stored indirection information from the first level main memory to the second level main memory before a transition to a low power state.

6 . The memory controller of claim 5 , further configured to initiate an additional transfer of user data currently not stored in the second level main memory from a central processing unit or the first level main memory to the second level main memory.

7 . The memory controller of claim 5 , further configured to initiate a transfer of the indirection information from the second level main memory to the first level main memory upon resume from the low power state.

8 . A memory controller for wear-leveled memory, wherein the memory controller is configured to
receive, from a remote memory controller, a memory request for the wear-leveled memory, the received memory request including information on a physical address of the wear-leveled memory; and access the wear-leveled memory at the physical address of the received memory request.

9 . The memory controller of claim 8 , further configured to
modify, according to a wear leveling scheme, indirection information stored in the wear-leveled, the indirection information a mapping between at least one logical address and at least one corresponding physical address of the wear-leveled memory.

10 . The memory controller of claim 8 , wherein the received memory request further includes an indirection hint providing a potential mapping between the physical address and a received logical address generated by the remote memory controller, wherein the memory controller is further configured to compare the indirection hint against actual indirection information stored in the wear-leveled memory, the actual indirection information providing an actual mapping between the received logical address and a corresponding physical addresses of the wear-leveled memory.

11 . The memory controller of claim 10 , further configured to
access user data at the physical address of the received memory request, if the indirection hint corresponds to the actual indirection information of the wear-leveled memory, or access user data at a physical address based on the actual indirection information stored in the wear-leveled memory, if the indirection hint differs from the actual indirection information of the wear-leveled memory.

12 . The memory controller of claim 8 , further configured to issue a notification message indicative of an updated mapping between at least one logical memory address and at least one corresponding physical memory address of the wear-leveled memory.

13 . The memory controller of claim 12 , further configured to issue the notification message using an interrupt or an asynchronous notification.

14 . A memory system, comprising:
main memory comprising
first level main memory of volatile memory;
second level main memory of wear-leveled memory;
wherein the first level main memory is configured to store indirection information providing a mapping between at least one logical address and at least one physical address of the second level main memory; and
at least one memory controller configured to initiate an access of a physical memory unit of the second level main memory using the indirection information stored in the first level main memory.

15 . The memory system of claim 14 , wherein the second level main memory comprises a second level main memory controller configured to modify, according to a wear leveling scheme, a mapping between at least one logical address and at least one corresponding physical address of the second level main memory.

16 . The memory system of claim 14 , wherein the memory controller is configured to compare indirection information of the first level main memory used to access the second level main memory against actual indirection information stored in the second level main memory.

17 . The memory system of claim 16 , wherein the memory controller is configured to access user data at a physical address based on the actual indirection information stored in the second level main memory, if the indirection information of the first level main memory differs from the actual indirection information of the second level main memory.

18 . The memory system of claim 14 , wherein the second level main memory or a controller thereof is configured to issue a notification message indicative of an updated mapping between at least one logical memory address and at least one corresponding physical memory address of the second level main memory to generate updated indirection information in the first level main memory.

19 . The memory system of claim 14 , wherein the memory controller is configured to initiate a transfer of the stored indirection information from the first level main memory to the second level main memory before a transition to a low power state where content of the first level main memory of volatile memory and wherein the memory controller is configured to initiate a transfer of the indirection information back from the second level main memory to the first level main memory upon resume from the low power state.

20 . The memory system of claim 14 , further comprising:
a central processing unit, wherein the central processing unit, the memory controller and the first level main memory are commonly integrated in a first semiconductor package, and wherein the second level main memory is implemented in a separate second semiconductor package and
a network interface communicatively coupled to the central processing unit.

21 . The memory system of claim 14 , wherein an access latency of the first level main memory is

Assignees

• Intel Corp

Inventors

• Royer Jr Robert J
• Fanning Blaise

Classifications

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G06F2212/7207

  management of metadata or control data · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title

• G06F2212/466

  Metadata, control data · CPC title