Adjustable error protection for stored data

Patent metadata

Field	Value
Publication number	US-2017147429-A1
Application number	US-201514947801-A
Country	US
Kind code	A1
Filing date	Nov 20, 2015
Priority date	Nov 20, 2015
Publication date	May 25, 2017
Grant date	—

Abstract

An apparatus is described that includes a semiconductor chip having memory controller logic circuitry. The memory controller logic circuitry has compression circuitry to compress a cache line data structure to be written into a system memory. The memory controller logic circuitry has adjustable length ECC information generation circuitry to generate an amount of ECC information for the cache line data structure based on an amount of compression applied to the cache line data structure by the compression circuitry. The memory controller logic having circuitry to implement a write process sequence for the cache line data structure that is specific for the cache line data structure's amount of compression and/or amount of ECC information and to implement a different write process sequence that is specific for another cache line data structure having a different amount of compression and/or ECC information as the cache line data structure.

First claim

1 . An apparatus, comprising:
a semiconductor chip comprising memory controller logic circuitry, said memory controller logic circuitry comprising: a) compression circuitry to compress a cache line data structure to be written into a system memory; b) adjustable length ECC information generation circuitry to generate an amount of ECC information for the cache line data structure based on an amount of compression applied to the cache line data structure by the compression circuitry; c) circuitry to implement a write process sequence for the cache line data structure that is specific for the cache line data structure's amount of compression and/or amount of ECC information and to implement a different write process sequence that is specific for another cache line data structure having a different amount of compression and/or ECC information as the cache line data structure.

2 . The apparatus of claim 1 wherein the cache line data structure comprises a super cache line.

3 . The apparatus of claim 1 wherein the memory controller comprises a far memory controller and the cache line is to be written into a non volatile system memory region.

4 . The apparatus of claim 1 wherein the non volatile system memory region is composed of any of the following:
a phase change memory;
a ferro-electric random access memory;
a magnetic random access memory;
a spin transfer torque random access memory;
a resistor random access memory;
a memristor memory;
a universal memory;
a Ge2Sb2Te5 memory;
a programmable metallization cell memory;
an amorphous cell memory;
an Ovshinsky memory.

5 . The apparatus of claim 1 wherein the write process sequence comprises a write of the cache line data structure to a region of the system memory having a first bit error rate and the different write process sequence comprise a write of the another cache line data structure to another region of the system memory having a second bit error rate.

6 . The apparatus of claim 5 wherein the first bit error rate is higher than the second bit error rate and the cache line data structure has more ECC information than the another cache line data structure.

7 . The apparatus of claim 1 wherein the write process sequence comprises creation of an error correction pointer data structure for the cache line data structure and the different write process sequence comprises no creation of an error correction pointer data structure for the another cache line data structure because the cache line data structure has less compression and/or less ECC information than the another cache line data structure.

8 . The apparatus of claim 1 wherein the write process sequence comprises creation of a larger combination of data and ECC information and the different write sequence comprises creation of a smaller combination of data and ECC information because the cache line data structure had less compression than the another cache line data structure.

9 . A computing system, comprising:
a) a plurality of processors; b) a multi-level system memory coupled to the plurality of processors; c) a memory controller coupled between a system memory level of the multi-level system memory and the plurality of processors, the memory controller comprising:
i) compression circuitry to compress a cache line data structure to be written into the system memory level;
ii) adjustable length ECC information generation circuitry to generate an amount of ECC information for the cache line data structure based on an amount of compression applied to the cache line data structure by the compression circuitry;
iii) circuitry to implement a write process sequence for the cache line data structure that is specific for the cache line data structure's amount of compression and/or amount of ECC information and to implement a different write process sequence that is specific for another cache line data structure having a different amount of compression and/or ECC information as the cache line data structure.

10 . The apparatus of claim 9 wherein the cache line data structure comprises a super cache line.

11 . The apparatus of claim 9 wherein the memory controller comprises a far memory controller and the cache line is to be written into a non volatile system memory region.

12 . The apparatus of claim 9 wherein the non volatile system memory region is composed of any of the following:
a phase change memory;
a ferro-electric random access memory;
a magnetic random access memory;
a spin transfer torque random access memory;
a resistor random access memory;
a memristor memory;
a universal memory;
a Ge2Sb2Te5 memory;
a programmable metallization cell memory;
an amorphous cell memory;
an Ovshinsky memory.

13 . The apparatus of claim 9 wherein the write process sequence comprises a write of the cache line data structure to a region of the system memory having a first bit error rate and the different write process sequence comprise a write of the another cache line data structure to another region of the system memory having a second bit error rate.

14 . The apparatus of claim 13 wherein the first bit error rate is higher than the second bit error rate and the cache line data structure has more ECC information than the another cache line data structure.

15 . The apparatus of claim 9 wherein the write process sequence comprises creation of an error correction pointer data structure for the cache line data structure and the different write process sequence comprises no creation of an error correction pointer data structure for the another cache line data structure because the cache line data structure has less compression and/or less ECC information than the another cache line data structure.

16 . The apparatus of claim 9 wherein the write process sequence comprises creation of a larger combination of data and ECC information and the different write sequence comprises creation of a smaller combination of data and ECC information because the cache line data structure had less compression than the another cache line data structure.

17 . The apparatus of claim 9 , further comprising one or more of:
a network interface communicatively coupled to the plurality of processors, a battery communicatively coupled to the plurality of processors, and a display communicatively coupled to the plurality of processors.

18 . A method, comprising:
compressing a first cache line data structure; calculating a first amount of ECC information for the first cache line data structure based on the amount of compression applied to the first cache line data structure; writing the first cache line data structure into a system memory according to a first write sequence process that is based at least in part on the amount of compression and/or ECC information of the first cache line data structure; compressing a second cache line data structure; calculating a second amount of ECC information for the second cache line data structure based on the amount of compression applied to the second cache line data structure; and, writing the second cache line data structure into the system memory according to a second write sequence process that is based at least in part of the amount of compression and/or ECC information of the second cache line data structure, the first write sequence being different than the second write sequence because the amount of compression and/or ECC information of the first cache line data structure is different than the amount of compression and/or ECC information of the second cache line data st

Assignees

• Intel Corp

Inventors

• Motwani Ravi

Classifications

• H03M13/356

  Unequal error protection [UEP] · CPC title

• H03M13/6312 Primary

  Error control coding in combination with data compression · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0661

  Format or protocol conversion arrangements · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title