Method for forming semiconductor structure and semiconductor structure

Patent metadata

Field	Value
Publication number	US-2022052150-A1
Application number	US-202117445993-A
Country	US
Kind code	A1
Filing date	Aug 26, 2021
Priority date	Aug 13, 2020
Publication date	Feb 17, 2022
Grant date	—

Abstract

A method for forming a semiconductor structure includes providing a semiconductor substrate, which at least includes discrete conducting layers in the semiconductor substrate; forming discretely arranged supporting structures on the semiconductor substrate, capacitor openings being included between the supporting structures; forming lower electrodes on sidewalls of the supporting structures, the lower electrodes being electrically connected with the conducting layers; forming a capacitor dielectric layer covering tops of the supporting structures, sidewalls of the lower electrodes, and bottoms of the capacitor openings; and forming an upper electrode covering the capacitor dielectric layer, to form capacitor structures.

First claim

What is claimed is:

1 . A method for forming a semiconductor structure, comprising:
providing a semiconductor substrate, which at least comprises discrete conducting layers in the semiconductor substrate; forming discretely arranged supporting structures on the semiconductor substrate, capacitor openings being comprised between the supporting structures; forming lower electrodes on sidewalls of the supporting structures, the lower electrodes being electrically connected with the conducting layers; forming a capacitor dielectric layer covering tops of the supporting structures, sidewalls of the lower electrodes, and bottoms of the capacitor openings; and forming an upper electrode covering the capacitor dielectric layer, to form capacitor structures.

2 . The method for forming a semiconductor structure of claim 1 , wherein said forming the discretely arranged supporting structures on the semiconductor substrate comprises:
forming a supporting layer on the semiconductor substrate; and patterning the supporting layer to form the capacitor openings, the remaining supporting layer forming the supporting structures.

3 . The method for forming a semiconductor structure of claim 2 , wherein the capacitor openings at least expose a part of a top surface of each discrete conducting layer.

4 . The method for forming a semiconductor structure of claim 1 , further comprising:
before forming the supporting structures, forming a bottom conducting layer on the semiconductor substrate, the bottom conducting layer being electrically connected with the conducting layers, wherein forming the supporting structures comprises: forming the discretely arranged supporting structures on the bottom conducting layer; and after forming the lower electrodes and before forming the capacitor dielectric layer, etching away the bottom conducting layer exposed from the bottom of the capacitance openings.

5 . The method for forming a semiconductor structure of claim 1 , wherein each of the supporting structures is a stacked structure formed by sequential stacking.

6 . The method for forming a semiconductor structure of claim 5 , wherein the stacked structure comprises a bottom supporting layer and a filling layer that are formed by sequentially stacking.

7 . The method for forming a semiconductor structure of claim 2 , wherein said patterning the supporting layer to form a plurality of discrete capacitor openings comprises:
sequentially forming a mask layer and a patterned photoresist layer on the supporting layer; patterning the mask layer based on the photoresist layer; and etching the supporting layer based on the patterned mask layer to form the capacitor openings.

8 . The method for forming a semiconductor structure of claim 1 , wherein said forming the lower electrodes electrically connected with the conducting layers on the sidewalls of the supporting structures comprises:
forming a top conducting layer on the tops and sidewalls of the supporting structures and the bottoms of the capacitor openings; and removing the top conducting layer on the tops of the supporting structure and the bottoms of the capacitor openings to form the lower electrodes on the sidewalls of the supporting structures.

9 . The method for forming a semiconductor structure of claim 8 , wherein a process for removing the top conducting layer on the tops of the supporting structures comprises chemical mechanical polishing.

10 . The method for forming a semiconductor structure of claim 1 , wherein said forming the upper electrode covering the capacitor dielectric layer comprises:
forming a first conducting layer covering the capacitor dielectric layer; and forming a second conducting layer filling gaps between the first conducting layer, a top surface of the second conducting layer being parallel to a top surface of the first conducting layer on the supporting structure, and a height of the top surface of the second conducting layer being greater than a height of the top surface of the first conducting layer on the supporting structure.

11 . The method for forming a semiconductor structure of claim 10 , wherein said forming the second conducting layer filling the gaps between the first conducting layer comprises:
forming a second conducting film filling the gaps between the first conducting layer, a height of a top surface of the second conducting film being greater than a height of the top surface of the first conducting layer on the supporting structure; and performing chemical mechanical polishing on the top surface of the second conducting film to form the second conducting layer.

12 . A semiconductor structure, comprising:
a semiconductor substrate, wherein at least discrete conducting layers are comprised in the semiconductor substrate; multiple discrete supporting structures, located on the semiconductor substrate; and capacitor structures supported by the supporting structures, wherein each capacitor structure comprises: a lower electrode, located on a sidewall of the supporting structure and electrically connected with a conducting layer; a capacitor dielectric layer, located at a top of the supporting structure, a sidewall of the lower electrode, and a bottom of a gap between the supporting structures; and an upper electrode, located on the capacitor dielectric layer.

13 . The semiconductor structure of claim 12 , wherein gaps between the supporting structures at least expose a part of a top surface of each discrete conducting layer; and the lower electrode is configured to connect to the exposed top surface of the discrete conducting layer.

14 . The semiconductor structure of claim 12 , wherein the upper electrode comprises:
a first conducting layer, located on the capacitor dielectric layer; and a second conducting layer, filling gaps between the first conducting layer, a height of a top surface of the second conducting layer being greater than a height of a top surface of the first conducting layer on the supporting structure.

15 . The semiconductor structure of claim 12 , further comprising a bottom conducting layer, located between the semiconductor substrate and the supporting structures and configured to electrically connect the conducting layers and the lower electrodes.

Assignees

• Changxin Memory Tech Inc

Inventors

• Wang Lingxiang

Classifications

• H10D1/043

  using patterning processes to form electrode extensions, e.g. etching · CPC title

• H10D1/716 Primary

  having vertical extensions · CPC title

• H10D1/042 Primary

  using deposition processes to form electrode extensions · CPC title

• H01L27/108

  Electricity · mapped topic

• H01L28/91 Primary

  Electricity · mapped topic