Selective metal removal for conductive interconnects in integrated circuitry

Patent metadata

Field	Value
Publication number	US-2022051896-A1
Application number	US-202117510219-A
Country	US
Kind code	A1
Filing date	Oct 25, 2021
Priority date	Sep 30, 2016
Publication date	Feb 17, 2022
Grant date	—

Abstract

Techniques for selectively removing a metal or conductive material during processing of a semiconductor die for high-voltage applications are provided. In some embodiments, the techniques treat a metallized semiconductor die to transfer a feature from a patterned photoresist layer deposited on the metallized semiconductor die. In addition, the patterned metallized semiconductor die can be subjected to an etch process to remove an amount of metal according to the feature in the pattern, resulting in a treated metallized semiconductor die that defines an opening adjacent to at least a pair of neighboring metal interconnects in the die. The treated metallized semiconductor die can be further treated to backfill the opening with a dielectric material, resulting in a metallized semiconductor die having a backfilled dielectric member. Such a metallized semiconductor die can be further processed according to a process of record until metallization, after which additional selective removal of another amount of metal can be implemented. Semiconductor dies having neighboring metal interconnects separated by backfilled dielectric regions also are provided.

First claim

What is claimed is:

1 . An integrated circuit (IC) structure, comprising:
a first conductive interconnect line embedded to a depth in one or more first dielectric materials, wherein the first conductive interconnect line has a first upper surface; a second conductive interconnect line substantially parallel to the first conductive interconnect line and embedded to the depth in the one or more first dielectric materials, wherein the second conductive interconnect line has a second upper surface substantially coplanar with the first upper surface; and a second dielectric material between, and parallel with, the first and second conductive interconnect lines, wherein the second dielectric material is embedded to the depth within the one or more first dielectric materials.

2 . The IC structure of claim 1 , further comprising a third conductive interconnect line between, and parallel with, the first and second conductive interconnect lines, and embedded to the depth in the one or more first dielectric materials, wherein a first end of the third conductive interconnect line is spaced apart from a second end of the second dielectric material with the one or more first dielectric materials between the first and second ends.

3 . The IC structure of claim 2 , wherein second dielectric material has substantially the same lateral width as that of the third conductive interconnect line.

4 . The IC structure of claim 2 , wherein first, second and third interconnect lines have substantially the same composition.

5 . The IC structure of claim 4 , wherein the first and second conductive interconnect features comprise titanium, tungsten, tantalum, aluminum, copper, ruthenium, cobalt, chromium, iron, palladium, molybdenum, manganese, vanadium, gold, silver, or niobium.

6 . The IC structure of claim 1 , wherein a chemical composition of the second dielectric material is different than that of at least one of the one or more first dielectric materials.

7 . The IC structure of claim 1 , wherein a chemical composition of the second dielectric material is the same as that of at least one of the one or more first dielectric materials.

8 . The IC structure of claim 1 , wherein the second dielectric material has a third upper surface substantially coplanar with the first and second upper surfaces.

9 . The IC structure of claim 1 , wherein the one or more first dielectric materials comprise:
a bottom dielectric material in contact with a bottom of the first and second conductive interconnect lines; and a top dielectric material over the bottom dielectric material, and in contact with a sidewall of first and second interconnect lines.

10 . The IC structure of claim 9 , wherein a bottom of the second dielectric material is in contact with the bottom dielectric material and a sidewall of the second dielectric material is in contact with the top dielectric material.

11 . An integrated circuit (IC) structure, comprising:
a first conductive interconnect feature embedded to a depth in a first dielectric material, wherein the first conductive interconnect feature has a first upper surface; a second conductive interconnect feature substantially parallel to the first conductive interconnect feature and embedded to the depth in the first dielectric material, wherein the second conductive interconnect feature has a second upper surface substantially coplanar with the first upper surface; a second dielectric material over the first and second conductive interconnect features; and a third dielectric material between, and parallel with, the first and second conductive interconnect features, wherein the third dielectric material is embedded to the depth within the first dielectric material, and wherein the second dielectric material has a third upper surface substantially coplanar with an upper surface of the second dielectric material.

12 . The IC structure of claim 11 , wherein a first portion of the third dielectric material adjacent to the second dielectric material has a first lateral width, and wherein a second portion of the third dielectric material adjacent to the first dielectric material has a second lateral width, smaller than the first lateral width.

13 . The IC structure of claim 12 , wherein the second lateral width is substantially equal to a lateral width of the first and second conductive interconnect features.

14 . The IC structure of claim 11 , wherein the first and second conductive interconnect features comprise titanium, tungsten, tantalum, aluminum, copper, ruthenium, cobalt, chromium, iron, palladium, molybdenum, manganese, vanadium, gold, silver, or niobium.

15 . The IC structure of claim 11 , wherein the first dielectric material and third dielectric material comprises silicon and oxygen.

16 . The IC structure of claim 11 , wherein the second dielectric material comprises silicon and nitrogen.

17 . A computing device, comprising:
a processor chip; and a memory chip, wherein at least one of the processor chip or memory chip comprises:
a first conductive interconnect line embedded to a depth in one or more first dielectric materials, wherein the first conductive interconnect line has a first upper surface;
a second conductive interconnect line substantially parallel to the first conductive interconnect line and embedded to the depth in the one or more first dielectric materials, wherein the second conductive interconnect line has a second upper surface substantially coplanar with the first upper surface; and
a second dielectric material between, and parallel with, the first and second conductive interconnect lines, wherein the second dielectric material is embedded to the depth within the one or more first dielectric materials.

18 . The computing device of claim 17 , further comprising a wireless communication chip.

19 . The computing device of claim 17 , wherein the processor chip is a reduced instruction set computer (RISC) processor, a complex instruction set computer (CISC) processor chip.

20 . The computing device of claim 17 , memory chip comprises a dynamic RAM (DRAM) chip, static RAM (SRAM) chip, or flash memory chip.

Assignees

• Intel Corp

Inventors

• Lin Kevin
• Kasim Rahim
• Chandhok Manish
• Gstrein Florian

Classifications

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/427 Primary

  Power or ground buses · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title