Methods and apparatuses to form self-aligned caps

Patent metadata

Field	Value
Publication number	US-2015270224-A1
Application number	US-201514675613-A
Country	US
Kind code	A1
Filing date	Mar 31, 2015
Priority date	Nov 4, 2011
Publication date	Sep 24, 2015
Grant date	—

Abstract

At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

First claim

What is claimed is:

1 . An apparatus, comprising:
a substrate comprising silicon; an interlayer dielectric layer over the substrate, the interlayer dielectric layer comprising silicon, oxygen, and carbon, the interlayer dielectric layer having a top boundary; a trench in the interlayer dielectric layer, the trench having internal sidewalls; a barrier layer comprising tantalum and nitrogen on the internal sidewalls of the trench; a conductive material in the trench, the barrier layer between the conductive material and the interlayer dielectric layer, the conductive material comprising copper and cobalt; and a capping region at the top of the conductive material, the capping region comprising cobalt, a top of the capping region near the interlayer dielectric layer being no higher than the top boundary of the interlayer dielectric layer that is near the capping region.

2 . The apparatus of claim 1 , wherein the dielectric layer comprises a low-k material.

3 . The apparatus of claim 1 , wherein the substrate comprises silicon.

4 . The apparatus of claim 1 , wherein the barrier layer comprises tantalum and nitrogen.

5 . The apparatus of claim 1 , wherein the capping region comprises cobalt.

6 . The apparatus of claim 5 , wherein the dielectric material comprises silicon, carbon, and oxygen, and the barrier layer comprises tantalum and nitrogen.

7 . An apparatus, comprising:
a substrate comprising a semiconductor material; a dielectric layer over the substrate, the dielectric layer having a top boundary; a plurality of trenches in the dielectric layer, the plurality of trenches having sidewalls; a barrier layer on the sidewalls of at least some of the plurality of trenches; conductive material in the at least some of the plurality of trenches, the barrier layer being between the conductive material and the sidewalls, the conductive material being no higher than the top boundary of the dielectric layer at a location near to the conductive material, the conductive material comprising copper and cobalt; and a capping region on the conductive material, the capping region being no higher than the top boundary of the dielectric layer that is near to the capping region.

8 . The apparatus of claim 7 , wherein the dielectric layer comprises a silicon, oxygen, and carbon.

9 . The apparatus of claim 8 , wherein the dielectric layer comprises carbon doped silicon oxide.

10 . An apparatus, comprising:
at least one first conductive line in a dielectric layer over a substrate to form a channel comprising a dielectric sidewall, and a first capping layer selectively deposited on the at least one first conductive line and on the dielectric sidewall to prevent electromigration.

11 . The apparatus of claim 10 , wherein the first capping layer is self-aligned to the first conductive line.

12 . The apparatus of claim 10 , wherein the first conductive line comprises a first metal, and the first capping layer comprises a second metal other than the first metal.

13 . The apparatus of claim 10 , further comprising
a second capping layer selectively deposited on the second conductive line within second sidewalls of the dielectric layer, the second conductive line being at a first spacing from the at least one first conductive line, and wherein the second capping layer is at the first spacing from the first capping layer.

14 . The apparatus of claim 10 , wherein the at least first conductive line is at a depth from 5 nanometers to 50 nanometers from a top surface of the dielectric layer.

15 . The apparatus of claim 10 , wherein the first conductive line is at a depth from a top surface of the dielectric layer that is from 10% to 50% of the thickness of the first conductive line.

16 . The apparatus of claim 10 , wherein the at least one first conductive line is an interconnect incorporated into a data processing system.

17 . The apparatus of claim 10 , wherein a spacing between the at least one first conductive line and a second conductive line in the dielectric layer is from 5 nm to 500 nm.

Assignees

• Intel Corp

Inventors

• Boyanov Boyan
• Singh Kanwal Jit

Classifications

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/056 Primary

  by filling conductive material into holes, grooves or trenches · CPC title