Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2022028885-A1
Application number	US-202117203122-A
Country	US
Kind code	A1
Filing date	Mar 16, 2021
Priority date	Jul 24, 2020
Publication date	Jan 27, 2022
Grant date	—

Abstract

A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a first stacked structure on a substrate, the first stacked structure including first gate electrodes stacked in a first direction; a first supporter layer on the first stacked structure, the first supporter layer divided by a first cut pattern; a second stacked structure on the first supporter layer, the second stacked structure including second gate electrodes stacked in the first direction; a block cut structure extending in a second direction intersecting the first direction and cutting at least one of the second stacked structure or the first stacked structure; a second supporter layer on the second stacked structure and divided by a second cut pattern; and a channel structure including a lower channel structure penetrating the first stacked structure, and an upper channel structure penetrating the first supporter layer and the second stacked structure, wherein a width of an upper face of the channel structure in a third direction intersecting the second direction is greater than a width of a lower surface of the channel structure in the third direction, a width of an uppermost face of the lower channel structure in the second direction is greater than a width of a lowermost face of the upper channel structure in the second direction, the first stacked structure includes a first stack and a second stack which are at least partially divided by the block cut structure, the second stacked structure includes a third stack on the first stack, and a fourth stack on the second stack, the third stack and the fourth stack separated by the block cut structure, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern of the first supporter layer includes a first connection on the block cut structure, the first connection connecting the first supporter layer on the first stack with the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure, the second connection connecting the second supporter layer on the third stack with the fourth stack.

2 . The semiconductor memory device of claim 1 , wherein the first connection includes n first sub-connections spaced apart from each other in the second direction,
the second connection includes m second sub-connections spaced apart from each other in the second direction, and n and m are integers greater than or equal to 1, and n is greater than m.

3 . The semiconductor memory device of claim 1 , wherein the first connection includes n first sub-connections spaced apart from each other in the second direction,
the second connection includes m second sub-connections spaced apart from each other in the second direction, n and m are integers greater than or equal to 1, and n is less than M.

4 . The semiconductor memory device of claim 1 , wherein the block cut structure includes a first sub-cut structure which cuts the first stacked structure, the first cut pattern and the second stacked structure, and a second sub-cut structure which cuts the second stacked structure, and
the second sub-cut structure is on the first connection.

5 . The semiconductor memory device of claim 4 , wherein the first sub-cut structure and the second sub-cut structure alternate in the second direction.

6 . The semiconductor memory device of claim 4 , wherein the first stacked structure further includes a first connection stack connecting the first stack and the second stack, and
the first connection is on the first connection stack.

7 . The semiconductor memory device of claim 4 , wherein a width of an upper face of the block cut structure in the third direction is greater than a width of a lower surface of the block cut structure in the third direction.

8 . The semiconductor memory device of claim 1 , wherein the block cut structure includes,
(a) a first sub-cut structure cutting the first stacked structure, the first cut pattern, and the second stacked structure, (b) a second sub-cut structure cutting the second stacked structure, and (c) a third sub-cut structure cutting the first stacked structure, wherein the first sub-cut structure and the third sub-cut structure are spaced apart from each other in the first direction by the first supporter layer.

9 . The semiconductor memory device of claim 8 , wherein a width of the upper face of the upper face of the third sub-cut structure in the third direction is greater than a width of the lower face of the second sub-cut structure in the third direction.

10 . The semiconductor memory device of claim 8 , wherein the first sub-cut structure includes
(a) a lower cut structure cutting the first cut pattern and the first stacked structure, and (b) an upper cut structure cutting the second stacked structure, wherein a width of an uppermost face of the lower cut structure in the third direction is greater than a width of a lowermost face of the upper cut structure in the third direction.

11 . The semiconductor memory device of claim 8 , wherein the lower channel structure includes
(a) a first channel pattern penetrating the first stacked structure, (b) a first information storage film interposed between the first channel pattern and at least one of the first gate electrodes, and (c) a first channel pad placed on the first channel pattern, and the upper channel structure includes, (d) a second channel pattern on the first channel pad and penetrating the first supporter layer and the second stacked structure, (e) a second information storage film interposed between the first supporter layer and at least one of the second gate electrodes, and (f) a second channel pad on the second channel pattern.

12 . The semiconductor memory device of claim 1 , wherein at least a part of the second connection overlaps the first connection in the first direction.

13 . The semiconductor memory device of claim 1 , wherein the first supporter layer includes a first material, and the second supporter layer includes a second material different from the first material.

14 . A semiconductor memory device comprising:
a first stacked structure on a substrate, the first stacked structure including first gate electrodes stacked in a first direction; a first supporter layer on the first stacked structure; a second stacked structure on the first stacked structure, the second stacked structure including second gate electrodes stacked in the first direction; a plurality of first sub-cut structures cutting the first stacked structure and the second stacked structure and arranged in a second direction intersecting the first direction; a second sub-cut structure between the first sub-cut structures, the first sub-cut structures being spaced apart from each other in the second direction and being among the plurality of first sub-cut structures, the second sub-cut structure cutting the second stacked structure; a channel structure which including lower channel structure penetrating the first stacked structure and an upper channel structure penetrating the first supporter layer and the second stacked structure, wherein side walls of the channel structure have a step; and a second supporter layer on the second stacked structure, wherein the first supporter layer includes a first cut pattern through which the plurality of first sub-cut structures penetrates, the second supporter layer includes a second cut pattern which exposes at least a part of upper faces of the plurality of first sub-cut structures and expos

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Ji Young
• Yang Woo Sung
• Hwang Sung-Min
• Sung Suk Kang
• Lim Joon-Sung

Classifications

• H01L27/11565

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L27/11519

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title