Memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2021335801-A1
Application number	US-202016855732-A
Country	US
Kind code	A1
Filing date	Apr 22, 2020
Priority date	Apr 22, 2020
Publication date	Oct 28, 2021
Grant date	—

Abstract

Provided is a memory device including a substrate, a stack structure, a first set of vertical channel structures, a second set of vertical channel structures, and a first slit. The stack structure is disposed on the substrate. The first and second sets of vertical channel structures are arranged along a Y direction and penetrate through the stack structure to contact the substrate. The first slit is disposed between the first and second sets of vertical channel structures, and penetrates through the stack structure to expose the substrate. The first slit includes a plurality of first sub-slits discretely disposed along a X direction.

First claim

1 . A memory device, comprising:
a stack structure, disposed on a substrate; a first set of vertical channel structures and a second set of vertical channel structures, arranged along a Y direction and penetrating through the stack structure to contact the substrate; and a first slit, disposed between the first and second sets of vertical channel structures, and penetrating through the stack structure to expose the substrate, wherein the first slit comprises a plurality of first sub-slits discretely disposed along a X direction.

2 . The memory device according to claim 1 , wherein the substrate comprises an array region and a stair-step region, the first and second sets of vertical channel structures are disposed on the substrate in the array region.

3 . The memory device according to claim 2 , further comprising a first string select line cut between the plurality of discrete first sub-slits.

4 . The memory device according to claim 3 , wherein the first string select line cut extends at least beyond a first column of contacts in the stair-step region.

5 . The memory device according to claim 3 , wherein the stack structure comprises a plurality of conductive layers and a plurality of dielectric layers stacked alternately along a Z direction, a topmost conductive layer is a string select line to control the switch of the first and second sets of vertical channel structures.

6 . The memory device according to claim 5 , further comprising:
a second string select line cut embedded in the string select line and extending along the X direction to divide the first set of vertical channel structures into two first groups; and a third string select line cut embedded in the string select line and extending along the X direction to divide the second set of vertical channel structures into two second groups.

7 . The memory device according to claim 2 , further comprising:
two second slits respectively disposed at a first side of the first set of vertical channel structures and a second side of the second set of vertical channel structure which opposite to the first side, and the two second slits penetrating through the stack structure to expose the substrate, wherein the two second slits continuously extend from the array region into the stair-step region along the X direction respectively.

8 . The memory device according to claim 7 , wherein a length of one of the two second slits is greater than a sum of lengths of the plurality of first sub-slits.

9 . The memory device according to claim 7 , wherein a ratio of a sum of lengths of the plurality of first sub-slits to a length of one of the two second slits is in a range of 0.35 to 0.9.

10 . The memory device according to claim 1 , further comprising:
a third set of vertical channel structures arranged along the Y direction with the first and second sets of vertical channel structures and penetrating through the stack structure to contact the substrate; a third slit, disposed between the second and third sets of vertical channel structures, and penetrating through the stack structure to expose the substrate, wherein the third slit comprises a plurality of third sub-slits discretely disposed along the X direction.

11 . The memory device according to claim 10 , further comprising:
a fourth string select line cut embedded in a string select line and disposed between the plurality of third sub-slits.

12 . A method of manufacturing a memory device, comprising:
forming a stack layer on a substrate, wherein the stack layer comprises a plurality of first materials and a plurality of second materials; forming a string select line cut extending along a X direction in a topmost second material; respectively forming a first set of vertical channel structures and a second set of vertical channel structures at two sides of the string select line cut, the first and second sets of vertical channel structures penetrating through the stack layer to contact the substrate; and forming a first slit between the first and second sets of vertical channel structures, wherein the first slit penetrates through the stack structure to expose the substrate, the first slit comprises a plurality of first sub-slits discretely disposed along the X direction, and the string select line cut is divided into a plurality of first string select line cuts by the firs slit, wherein the plurality of first string select line cuts is located between the plurality of first sub-slits and discretely disposed along the X direction.

13 . The method of manufacturing the memory device according to claim 12 , further comprising:
performing an etching process to remove the plurality of second materials, so as to form a plurality of gaps between the plurality of first materials; and forming a plurality of conductive layers in the plurality of gaps, so that the plurality of conductive layers surround the first and second sets of vertical channel structures.

14 . The method of manufacturing the memory device according to claim 12 , wherein the forming the string select line cut comprising:
forming a second string select line cut to divide the first set of vertical channel structures into two first groups; and forming a third string select line cut to divide the second set of vertical channel structures into two second groups.

15 . The method of manufacturing the memory device according to claim 14 , wherein the substrate comprises an array region and a stair-step region, the first and second sets of vertical channel structures are formed on the substrate in the array region, and the plurality of first string select line cuts and the first slit are formed to extend from the array region into the stair-step region.

16 . The method of manufacturing the memory device according to claim 15 , wherein the forming the first slit comprises:
respectively forming two second slits at a first side of the first set of vertical channel structures and a second side of the second set of vertical channel structure which opposite to the first side, the two second slits penetrating through the stack layer to expose the substrate, wherein the two second slits continuously extend from the array region into the stair-step region along the X direction respectively.

17 . The method of manufacturing the memory device according to claim 15 , wherein the forming the first and second sets of vertical channel structures comprises:
forming a plurality of sets of dummy vertical channel structures penetrating through the stack layer in the stair-step region to contact the substrate in the stair-step region.

18 . The method of manufacturing the memory device according to claim 12 , wherein the plurality of first string select line cuts and the plurality of second materials have different materials or materials with different etching selectivies.

19 . A memory device, comprising:
a stack structure, disposed on a substrate; a first set of vertical channel structures and a second set of vertical channel structures, arranged along a Y direction and penetrating through the stack structure to contact the substrate; and an isolation structure, disposed between the first and second sets of vertical channel structures, wherein the isolation structure comprises a plurality of sub-slits and a plurality of string select line cuts arranged alternately along a X direction.

20 . The memory device according to claim 19 , further comprising:
a second slit disposed at a first side of the first set of vertical channel structures and p

Assignees

• Macronix Int Co Ltd

Inventors

• Yang Chih-Kai
• Han Tzung-Ting

Classifications

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title