Three dimensional memory device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-2020258898-A1
Application number	US-201916273301-A
Country	US
Kind code	A1
Filing date	Feb 12, 2019
Priority date	Feb 12, 2019
Publication date	Aug 13, 2020
Grant date	—

Abstract

A three-dimensional memory device includes a substrate, conductive layers and insulating layers, a storage layer, a first channel, a second channel and a first conductive plug. The conductive layers and insulating layers are alternately stacked over the substrate to form a multi-layer stacked structure. The storage layer penetrates through the multi-layer stacked structure, and has a first string portion and a second string portion that are spaced from each other. The first channel is located on a lateral side of the first string portion. The second channel is located on a lateral side of the second string portion. The first channel and the second channel have an upper channel portion and a lower channel portion. The first conductive plug is interconnected between the upper channel portion and the lower channel portion.

First claim

1 . A three-dimensional (3D) memory device, comprising:
a substrate; a plurality of conductive layers and insulating layers alternately stacked over the substrate to form a multi-layer stacked structure; a storage layer penetrating through the multi-layer stacked structure, and having a first string portion and a second string portion that are spaced from each other; a first channel disposed on a lateral side of the first string portion, and the first string portion is disposed between the multi-layer stacked structure and the first channel; a second channel disposed on a lateral side of the second string portion, and the second string portion is disposed between the multi-layer stacked structure and the second channel, wherein the first channel and the second channel have an upper channel portion and a lower channel portion; a first conductive plug interconnected between the upper channel portion and the lower channel portion; and a second conductive plug above the multi-layer stacked structure, wherein the upper channel portion comprises an outer channel layer and an inner channel layer, the outer channel layer is disposed between the storage layer and the inner channel layer and spaced from the first conductive plug, wherein the inner channel layer is in contact with the second conductive plug.

2 . The 3D memory device of claim 1 further comprising an etch stop layer disposed in the multi-layer stacked structure and at a side of the first conductive plug.

3 . The 3D memory device of claim 1 further comprising a bottom channel, and the lower channel portions of the first channel and the second channel are U-shaped channel portions that are spaced from each other and connected to two opposite ends of the bottom channel.

4 . The 3D memory device of claim 1 , wherein the upper channel portion has a bottom end in contact with the first conductive plug.

5 . (canceled)

6 . The 3D memory device of claim 1 further comprising an etch stop layer above the multi-layer stacked structure and at a side of the second conductive plug.

7 . The 3D memory device of claim 1 , wherein the first conductive plug and the second conductive plug comprise doped poly silicon.

8 . (canceled)

9 . A three-dimensional (3D) memory device, comprising:
a substrate; a plurality of conductive layers and insulating layers alternately stacked over the substrate to form a multi-layer stacked structure; a storage layer penetrating through the multi-layer stacked structure, and having a first string portion and a second string portion that are spaced from each other; a first channel in contact with the first string portion; a second channel in contact with the second string portion; and a dielectric feature disposed between the first channel and the second channel, the dielectric feature having a lower portion and an upper portion, and a top of the lower portion having a cross section wider than that of a bottom of the upper portion wherein the first channel is disposed between the first string portion and the dielectric feature, the second channel is disposed between the second string portion and the dielectric feature.

10 . The 3D memory device of claim 9 , wherein the upper portion or the lower portion of the dielectric feature comprise a taper cross section.

11 . The 3D memory device of claim 9 , wherein each of the first and second channels has an upper channel portion and a lower channel portion.

12 . The 3D memory device of claim 11 further comprising a first conductive plug interconnected between the upper channel portion and the lower channel portion.

13 . The 3D memory device of claim 12 further comprising an etch stop layer disposed in the multi-layer stacked structure and aligned with the first conductive plug.

14 . The 3D memory device of claim 12 further comprising a second conductive plug above the multi-layer stacked structure and connected to the upper channel portion.

15 . The 3D memory device of claim 14 further comprising an etch stop layer above the multi-layer stacked structure and aligned with the second conductive plug.

16 . The 3D memory device of claim 14 wherein the first conductive plug and the second conductive plug comprise doped poly silicon.

17 - 20 . (canceled)

21 . The 3D memory device of claim 1 , wherein the inner channel layer of the first channel is spaced from the inner channel layer of the second channel.

22 . The 3D memory device of claim 12 , wherein the upper channel portion comprises an outer channel layer and an inner channel layer, the outer channel layer is disposed between the storage layer and the inner channel layer and spaced from the first conductive plug.

Assignees

• Macronix Int Co Ltd

Inventors

• Hu Chih-Wei
• Yeh Teng-Hao
• Jiang Yu-Wei

Classifications

• H10P50/283

  by chemical means · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title