Fusion of microprocessor store instructions

Patent metadata

Field	Value
Publication number	US-2022019436-A1
Application number	US-202016933241-A
Country	US
Kind code	A1
Filing date	Jul 20, 2020
Priority date	Jul 20, 2020
Publication date	Jan 20, 2022
Grant date	—

Abstract

Provided is a method for fusing store instructions in a microprocessor. The method includes identifying two instructions in an execution pipeline of a microprocessor. The method further includes determining that the two instructions meet a fusion criteria. In response to determining that the two instructions meet the fusion criteria, the two instructions are recoded into a fused instruction. The fused instruction is executed.

First claim

1 . A method comprising:
identifying two instructions in an execution pipeline of a microprocessor, wherein the two instructions include a first instruction and a second instruction; determining that the two instructions meet a fusion criteria, wherein determining that the two instructions meet the fusion criteria comprises determining that the first and second instructions have a same instruction form and store data in contiguous memory locations; recoding, in response to determining that the two instructions meet the fusion criteria, the two instructions into a fused instruction; and executing the fused instruction.

2 . The method of claim 1 , wherein determining that the two instructions meet the fusion criteria further comprises:
determining that the first and second instructions have a same instruction type, a same instruction length, and that they are consecutive instructions in a fetch queue.

3 . The method of claim 1 , wherein the method further comprises:
identifying an exception while executing the fused instruction; flushing the fused instruction; and re-fetching the two instructions.

4 . The method of claim 3 , wherein the method further comprises:
executing, after re-fetching the two instructions, the two instructions separately.

5 . The method of claim 3 , the method further comprising:
determining that the exception was related to the first instruction of the two instructions; and recording the exception against the first instruction.

6 . The method of claim 1 , wherein the first instruction was fetched before the second instruction, the method further comprising:
determining that the first instruction is to store data to a first area of memory; determining that the second instruction is to store data to a second area of memory that directly precedes the first area of memory; marking the fused instruction as reversed; and flipping an order of the first and second instructions in the fused instruction.

7 . The method of claim 1 , wherein the first and second instructions are D-form store instructions, and wherein determining that the two instructions meet the fusion criteria further comprises:
determining that the first and second store instructions have the same base register; determining a store length for the first and second instructions, wherein the store length is the same for both the first and second instructions; and determining that a difference between a first offset of the first instruction and a second offset of the second instruction is equal to the store length.

8 . A system comprising:
a processor configured to perform a method comprising: identifying two instructions in an execution pipeline of the processor, wherein the two instructions include a first instruction and a second instruction; determining that the two instructions meet a fusion criteria, wherein determining that the two instructions meet the fusion criteria comprises determining that the first and second instructions have a same instruction form and store data in contiguous memory locations; recoding, in response to determining that the two instructions meet the fusion criteria, the two instructions into a fused instruction; and executing the fused instruction.

9 . The system of claim 8 , wherein determining that the two instructions meet the fusion criteria further comprises:
determining that the first and second instructions have a same instruction type, a same instruction length, and that they are consecutive instructions in a fetch queue.

10 . The system of claim 8 , wherein the method further comprises:
identifying an exception while executing the fused instruction; flushing the fused instruction; and re-fetching the two instructions.

11 . The system of claim 10 , wherein the method further comprises:
executing, after re-fetching the two instructions, the two instructions separately.

12 . The system of claim 10 , the method further comprising:
determining that the exception was related to the first instruction; and recording the exception against the first instruction.

13 . The system of claim 8 , wherein the first instruction precedes the second instruction in a fetch queue, the method further comprising:
determining that the first instruction is to store data to a first area of memory; determining that the second instruction is to store data to a second area of memory that directly precedes the first area of memory; marking the fused instruction as reversed; and flipping an order of the first and second instructions in the fused instruction.

14 . The system of claim 8 , wherein the first and second instructions are D-form store instructions, and wherein determining that the two instructions meet the fusion criteria further comprises:
determining that the first and second instructions have the same base register; determining a store length for the first and second instructions, wherein the store length is the same for both the first and second instructions; and determining that a difference between a first offset of the first instruction and a second offset of the second instruction is equal to the store length.

15 . A processor comprising:
an instruction fetch unit configured to:
determine that two store instructions fetched from memory are fusible by determining that the two store instructions have a same instruction form, store data in contiguous memory locations, and are consecutive in a fetch queue; and
recode the two store instructions into a fused store instruction;
an instruction sequencing unit configured to:
receive the fused store instruction from the instruction fetch unit; and
store the fused store instruction as an entry in an issue queue, wherein a first half of the fused store instruction is stored to a first half of the issue queue, and a second half of the fused store instruction is stored to a second half of the issue queue; and
a load-store unit configured to:
receive the fused store instruction from the issue queue via a vector/scalar unit;
generate a store address using the first half of the fused store instruction;
store the store address in a store reorder queue; and
store data identified by the second half of the fused store instruction in a store data queue.

16 . The processor of claim 15 , wherein the load-store unit is further configured to:
identify an exception while executing the fused store instruction; flush the fused store instruction; and instruct the instruction fetch unit to re-fetch the two store instructions.

17 . The processor of claim 16 , wherein the processor is further configured to:
execute, after re-fetching the two store instructions, the two store instructions as separate instructions.

18 . The processor of claim 15 , wherein the two store instructions include a first store instruction and a second store instruction, and wherein determining that the two store instructions are fusible further comprises:
determining that the first and second store instructions have a same instruction type and a same instruction length.

19 . The processor of claim 15 , wherein the two store instructions include a first store instruction that was fetched before a second store instruction, and wherein the instruction fetch unit is further configured to:
determine that the first store instruction is configured to store data to a first area of memory; determine that the second store instruction is configured to store data to a second area of memory that directly precedes the first area of memo

Assignees

• IBM

Inventors

• Lloyd Bryan
• Chadha Sundeep
• Nguyen Dung Q
• Zoellin Christian Gerhard
• Thompto Brian W
• Levenstein Sheldon Bernard
• Williams Phillip G
• Cordes Robert A
• Chen Brian

Classifications

• G06F9/3858

  Result writeback, i.e. updating the architectural state or memory · CPC title

• G06F9/30181 Primary

  Instruction operation extension or modification · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/3814

  Implementation provisions of instruction buffers, e.g. prefetch buffer; banks · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title