Power management system switched capacitor voltage regulator with integrated passive device

Patent metadata

Field	Value
Publication number	US-2022014095-A1
Application number	US-202117383983-A
Country	US
Kind code	A1
Filing date	Jul 23, 2021
Priority date	Dec 24, 2018
Publication date	Jan 13, 2022
Grant date	—

Abstract

Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

First claim

What is claimed is:

1 . (canceled)

2 . A power management system comprising:
a voltage source; a plurality of circuit loads; a control circuit configured to:
read performance states, weighted energy use, and binned voltage information for the plurality of circuit loads;
determine a corresponding operating voltage for each circuit load of the plurality of circuit loads;
assign a highest priority to a circuit load with a highest energy usage of the plurality of circuit loads;
select a first switched capacitor voltage regulator (SCVR) conversion ratio mode and an SCVR voltage input value from the voltage source for the circuit load with the highest energy usage; and
select a second SCVR conversion ratio mode for a next highest energy usage circuit load at the SCVR voltage input value.

3 . The power management system of claim 2 , wherein the performance states, weighted energy use, and binned voltage information for the plurality of circuit loads is stored in in a look up table within the control circuit.

4 . The power management system of claim 2 , further comprising:
a first SCVR coupled to the voltage source and the highest energy usage circuit load to receive an input voltage from the voltage source corresponding to the SCVR voltage input value and supply a first output voltage to the highest energy usage circuit load.

5 . The power management system of claim 4 , further comprising:
a second SCVR coupled to the voltage source and next highest energy usage circuit load to receive the input voltage from the voltage source corresponding to the SCVR voltage input value and supply a second output voltage to the next highest energy usage circuit load.

6 . The power management system of claim 5 , further comprising a circuit board including:
a main power supply conductor connecting the voltage source to the first SCVR and the second SCVR; and an auxiliary power supply conductor connecting the voltage source to the first SCVR and the second SCVR.

7 . The power management system of claim 6 , wherein the voltage source includes a main voltage source connected to the main power supply conductor and an auxiliary voltage source connected to the auxiliary power supply conductor.

8 . The power management system of claim 7 , wherein the highest energy usage circuit load and the next highest energy usage circuit load are located within a same chip.

9 . The power management system of claim 7 , wherein the highest energy usage circuit load and the next highest energy usage circuit load are located within separate chips.

10 . The power management system of claim 2 , wherein the control circuit is further configured to perform sweep calculation to validate a weighted efficiency of the first SCVR conversion ratio mode, the SCVR voltage input value, and the second SCVR conversion ratio mode.

11 . The power management system of claim 2 , wherein the highest energy usage circuit load and the next highest energy usage circuit load are located within a same chip.

12 . The power management system of claim 2 , wherein the highest energy usage circuit load and the next highest energy usage circuit load are located within separate chips.

13 . The power management system of claim 2 , wherein the highest energy usage circuit load and the next highest energy usage circuit load are different cores of a system on chip.

14 . The power management system of claim 2 , wherein the highest energy usage circuit load and the next highest energy usage circuit load are a high performance CPU (PCPU) and an efficient CPU (ECPU).

15 . A method of operating a power management system comprising:
reading a corresponding performance state for a plurality of circuit loads, weighted energy, and binned voltage information; determine a corresponding operating voltage for each circuit load; assigning a highest priority to a circuit load with a highest energy usage of the plurality of circuit loads; selecting a first switched capacitor voltage regulator (SCVR) conversion ratio mode and an SCVR voltage input value for the highest energy usage circuit load; and selecting a second SCVR conversion ratio mode for a next highest energy usage circuit load at the SCVR voltage input value.

16 . The method of claim 15 , wherein the plurality of circuit loads is located within a same chip.

17 . The method of claim 16 , further comprising performing a sweep calculation to validate a weighted efficiency of the first SCVR conversion ratio mode, the SCVR voltage input value, and the second SCVR conversion ratio mode.

18 . The method of claim 15 , further comprising sending a voltage corresponding to the SCVR voltage input value to a first SCVR coupled to the voltage source and the highest energy usage circuit load, and to a second SCVR coupled to the voltage source and the next highest energy usage circuit load.

19 . The method of claim 18 , wherein the first SCVR conversion ratio mode and the second SCVR conversion ratio mode are different.

Assignees

• Apple Inc

Inventors

• Dabral Sanjay
• Secker David A
• Zhai Jun
• Schmitt Ralf M
• Ramachandran Vidhya
• Mao Wenjie

Classifications

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title