Selective etching process for SiGe and doped epitaxial silicon
US-12062571-B2 · Aug 13, 2024 · US
US2022013424A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2022013424-A1 |
| Application number | US-202117483312-A |
| Country | US |
| Kind code | A1 |
| Filing date | Sep 23, 2021 |
| Priority date | Jun 7, 2018 |
| Publication date | Jan 13, 2022 |
| Grant date | — |
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An apparatus includes a semiconductor-based substrate with a functional structure that is formed in or on the semiconductor-based substrate. The apparatus includes a frame structure surrounding the functional structure and includes a coating that covers the functional structure and is delimited by the frame structure.
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What is claimed is: 1 . A method for producing a structure, the method comprising: providing a semiconductor-based substrate having a functional structure that is arranged in or on the semiconductor-based substrate; arranging a frame structure such that the frame structure surrounds the functional structure; and arranging a coating such that the coating covers the functional structure and is delimited by the frame structure. 2 . The method as claimed in claim 1 , wherein arranging the coating comprises: providing a liquid comprising a coating material; arranging the liquid in an inner region of the frame structure such that the liquid completely covers the inner region; and drying the inner region such that the coating material is left behind as the coating. 3 . The method as claimed in claim 2 , wherein the coating material comprises a first coating material, further comprising: arranging a second liquid in the inner region after the inner region has dried, wherein the second liquid comprises a second coating material; and drying the inner region again, such that the second coating material forms a layer on the coating. 4 . The method as claimed in claim 1 , wherein the substrate comprises a semiconductor wafer, and wherein the method is performed repeatedly on a wafer level. 5 . A method, comprising: forming a functional structure in or on a semiconductor-based substrate; arranging a frame structure to surround the functional structure, wherein the frame structure comprises a first vertical sidewall and a second vertical sidewall; and arranging a coating to cover the functional structure and to be delimited by the frame structure, wherein the coating comprises a carbon nanomaterial ink, wherein the coating comprises at least one first planar layer having a planar top surface and a planar bottom surface and one second planar layer having a planar bottom surface, and wherein the at least one first planar layer and one second player layer are laterally delimited by the first vertical sidewall and the second vertical sidewall. 6 . The method as claimed in claim 5 , wherein the coating completely covers an inner region of the frame structure. 7 . The method as claimed in claim 5 , wherein the coating comprises a homogeneous coating. 8 . The method as claimed in claim 5 , wherein the frame structure is arranged on a substrate side, and wherein the frame structure protrudes with respect to a substrate surface. 9 . The method as claimed in claim 8 , wherein the frame structure has a height of at least 10 nm and at most 1000 μm. 10 . The method as claimed in claim 5 , wherein the frame structure is arranged on a substrate side, and wherein the frame structure forms a trench in the substrate side. 11 . The method as claimed in claim 10 , wherein the frame structure has a depth of at least 10 nm and at most 1000 μm. 12 . The method as claimed in claim 5 , wherein the coating comprises a hydrophilic coating material and wherein the frame structure comprises a hydrophobic material. 13 . The method as claimed in claim 5 , wherein the coating comprises a hydrophobic coating material and in which the frame structure comprises a hydrophilic material. 14 . The method as claimed in claim 5 , wherein the frame structure comprises a frame width between an inner side of the frame structure and an outer side of the frame structure having a dimension of at least 10 nm and at most 10 mm. 15 . The method as claimed in claim 5 , wherein the frame structure comprises an electrically conductive frame structure. 16 . The method as claimed in claim 5 , wherein the frame structure comprises at least one first layer and one second layer. 17 . The method as claimed in claim 5 , wherein the functional structure comprises an electrode structure. 18 . The method as claimed in claim 5 , wherein the functional structure provides an electrically conductive function and/or a protective function against mechanical and/or chemical influences. 19 . The method as claimed in claim 5 , comprising a chemosensor or a transistor. 20 . A method, comprising: forming a functional structure in or on a semiconductor-based substrate; arranging a frame structure to surround the functional structure, wherein the frame structure comprises a first vertical sidewall and a second vertical sidewall; and arranging a coating to cover the functional structure, the coating comprising a first planar layer having a planar top surface and a planar bottom surface and a second planar layer having a planar top surface and a planar bottom surface, wherein the first planar layer and the second planar layer are both laterally delimited by the first vertical sidewall and the second vertical sidewall of the frame structure.
Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating · CPC title
the encapsulations being in grooves in the semiconductor body · CPC title
the encapsulations being multilayered · CPC title
characterised by their materials · CPC title
the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title
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