Fatal error logging in a memory device

US2022012117A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2022012117-A1
Application numberUS-202117461527-A
CountryUS
Kind codeA1
Filing dateAug 30, 2021
Priority dateAug 19, 2019
Publication dateJan 13, 2022
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Devices and techniques for fatal error logging in a memory device are described herein. For example, a read request can be received for a component of the memory device. A fatal error indication of an error that prevents correct execution of read request can be detected. Diagnostic information for the failure indication can be collected. A response to the read request can then be made with a portion of the diagnostic information as payload instead of the user data that would have occupied the payload had the read succeeded. Metadata in the response can be used to communicate an error code.

First claim

Opening claim text (preview).

1 . (canceled) 2 . A NAND flash memory controller comprising: a host interface configured to communicate with a host device; an array interface configured to communicate with an array of NAND flash devices; and processing circuitry configured to: receive a read request, from the host interface, for a NAND flash device in the array of NAND flash devices; perform, through the array interface, a read of the NAND flash device; detect an error in response to the read; collect diagnostic information of the error; partition the diagnostic information into segments sized to a payload of a response to the read request; create the response and include a segment of the diagnostic information in the payload; and transmit, through the host interface, the response. 3 . The NAND flash memory controller of claim 2 , wherein segments of the diagnostic information are ordered by importance. 4 . The NAND flash memory controller of claim 3 , and wherein the segment of the diagnostic information is selected to be included in the response because the segment of the diagnostic information has a highest importance in the segments of the diagnostic information. 5 . The NAND flash memory controller of claim 2 , wherein the payload is encrypted. 6 . The NAND flash memory controller of claim 2 , wherein the processing circuitry is configured to: receive a second read request on the host interface; and respond to the second read request with a second segment of the diagnostic information as payload in a response to the second read request. 7 . The NAND flash memory controller of claim 6 , wherein the processing circuitry is configured to: test for the error after receiving the second read request; and respond to the second read request, via the host interface, with the second segment of the diagnostic information in response to the test indicating that the error is ongoing. 8 . The NAND flash memory controller of claim 6 , wherein the second read request does not specify the NAND flash device. 9 . The NAND flash memory controller of claim 8 , wherein each subsequent read request response includes a new segment of the diagnostic information as payload without regard to any NAND flash device specified in a subsequent read request until every segment of the diagnostic information has been transmitted. 10 . The NAND flash memory controller of claim 6 , wherein the second read request specifies the NAND flash device. 11 . The NAND flash memory controller of claim 10 , wherein the error includes the NAND flash device but does not include a second NAND flash device in the array of NAND flash devices. 12 . The NAND flash memory controller of claim 11 , wherein the NAND flash device and the second NAND flash device are blocks. 13 . The NAND flash memory controller of claim 10 , wherein a response by the processing circuitry to each subsequent read request, received from the host interface, that specifies the NAND flash device includes a new segment of the diagnostic information as payload. 14 . A non-transitory computer readable medium including instructions that, when executed by processing circuitry of a controller for a storage device, cause the memory controller to perform operations comprising: receiving a request to read data from a portion of the storage device; detecting an error during an attempt to perform the request to read the data; formulating a response to the request, the response using diagnostic information from the error as payload instead of the result from the attempt to read the data; and transmitting the response to the request to a requestor that made the request. 15 . The non-transitory computer readable medium of claim 14 , wherein the diagnostic information is larger than the payload, wherein the operations include segmenting the diagnostic information, each segment sized to fit a payload of a response, wherein a segment is used as the payload in the response. 16 . The non-transitory computer readable medium of claim 14 , wherein the operations include ordering the segments of the diagnostic information by importance. 17 . The non-transitory computer readable medium of claim 16 , and wherein the segment is selected to be included in the response because the segment of the diagnostic information has a highest importance in the segments of the diagnostic information. 18 . The non-transitory computer readable medium of claim 14 , wherein the payload is encrypted. 19 . The non-transitory computer readable medium of claim 14 , wherein the operations comprise: receiving a second read request; and responding to the second read request with a second segment of the diagnostic information as payload in a response to the second read request. 20 . The non-transitory computer readable medium of claim 19 , wherein the operations comprise: testing for the error after receiving the second read request; and responding to the second read request with the second segment of the diagnostic information in response to the test indicating that the error is ongoing. 21 . The non-transitory computer readable medium of claim 19 , wherein the second read request does not specify the same portion of the storage device. 22 . The non-transitory computer readable medium of claim 21 , wherein each subsequent read request response includes a new segment of the diagnostic information as payload without regard to any portion of the storage device specified in a subsequent read request until every segment of the diagnostic information has been transmitted. 23 . The non-transitory computer readable medium of claim 19 , wherein the second read request specifies the same portion of the storage device. 24 . The non-transitory computer readable medium of claim 23 , wherein the error pertains to the portion of the storage device but does not pertain to a second portion of the storage device. 25 . The non-transitory computer readable medium of claim 24 , wherein the first and second portions of the storage device are NAND flash blocks. 26 . The non-transitory computer readable medium of claim 23 , wherein a response to each subsequent read request that specifies the NAND flash device includes a new segment of the diagnostic information as payload.

Assignees

Inventors

Classifications

  • in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

  • Error or fault reporting or storing · CPC title

  • in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title

  • Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title

  • using arrangements adapted for a specific error detection or correction feature · CPC title

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What does patent US2022012117A1 cover?
Devices and techniques for fatal error logging in a memory device are described herein. For example, a read request can be received for a component of the memory device. A fatal error indication of an error that prevents correct execution of read request can be detected. Diagnostic information for the failure indication can be collected. A response to the read request can then be made with a po…
Who is the assignee on this patent?
Micron Technology Inc
What technology area does this patent fall under?
Primary CPC classification G06F11/0727. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Jan 13 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).