Error feedback and logging with memory on-chip error checking and correcting (ECC)

Patent metadata

Field	Value
Publication number	US-9880896-B2
Application number	US-201414320283-A
Country	US
Kind code	B2
Filing date	Jun 30, 2014
Priority date	Jan 30, 2014
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

Error checking and correcting (ECC) may be performed in an on-chip memory where an error is corrected by a controller and not the on-chip memory. The controller may be flagged to show that an error has occurred and where it has occurred in the memory. The controller may access ECC bits associated with the error and may fix incorrect data. The error checking may be done in parallel with read operations of the memory so as to lower latency.

First claim

What is claimed is:

1. A method comprising:
receiving, at a memory device including a memory array and a first controller, a first request for data, the first request for data received from a device and the first request for data associated with a memory location of the memory array;
in response to the first request for data, receiving read data responsive to a read operation performed at the memory location of the memory array;
transmitting the read data from the first controller to the device;
detecting, at the memory device, a data error corresponding to the read data;
in response to detecting the data error, wherein transmitting the read data and detecting the data error are performed in parallel operation at the memory device:
setting, at the memory device, an open drain driver pin of the memory device to indicate detection of the data error to the device; and
generating data correction information to enable the device to correct the data error corresponding to the read data;

after setting the open drain driver pin of the memory device, receiving a second request for data at the memory device from the device; and
in response to receiving the second request for data, transmitting the data correction information from the memory device to the device.

2. The method of claim 1 , wherein detecting the data error at the memory device comprises checking error correction code (ECC) bits corresponding to the read data.

3. The method of claim 1 , further comprising receiving a third request for data at the memory device corresponding to another memory location of the memory array, wherein the third request for data is received between receiving the first request for data and receiving the second request for data.

4. The method of claim 1 , wherein the data correction information comprises error information, and further comprising writing the error information to an error log of the memory device.

5. The method of claim 1 , wherein the data correction information comprises a read address of the memory array corresponding to the data error, error correction code (ECC) bits associated with the data error, an error syndrome corresponding to the data error, signal data, redundant bit data, or a combination thereof.

6. The method of claim 4 , wherein the device comprises a second controller that is external to the memory device.

7. The method of claim 1 , wherein the data correction information comprises corrected data.

8. The method of claim 7 , further comprising:
correcting, by the memory device, the data error; and
storing the corrected data at a register of the memory device.

9. The method of claim 1 , further comprising, in response to receiving the first request for data, determining whether corrected data associated with the memory location is stored at a register of the memory device.

10. The method of claim 1 , further comprising, in response to receiving the second request for data, determining whether a corrected version of the read data is stored at a register of the memory device.

11. The method of claim 1 , wherein a signal from the open drain driver pin of the memory device is detectable by a plurality of devices.

12. A method comprising:
receiving, at a first controller of a memory device from a second controller, a first request for data at a memory location of a memory array;
transmitting, from the first controller, read data corresponding to the memory location to the second controller in response to the first request for data;
detecting a data error associated with the read data, wherein transmitting the read data and detecting the data error are performed in parallel operation at the memory device;
after setting, at the memory device, an open drain driver pin to indicate detection of the data error associated with the read data, receiving a second request corresponding to the memory location, the second request for data received from the second controller; and
in response to receiving the second request, transmitting data correction information to the second controller, the data correction information to enable the second controller correct the data error associated with the read data.

13. The method of claim 12 , wherein the second controller is external to the memory device.

14. The method of claim 12 , further comprising, in response to receiving the first request for data, determining whether an address corresponding to the memory location is stored in a register of the memory device.

15. The method of claim 12 , further comprising setting the open drain driver pin to indicate the detection of the data error, the open drain driver pin shared by a plurality of devices including the second controller.

16. A method comprising:
receiving, at a first controller of a memory device from a second controller, a first request for data at a memory location of a memory array;
in response to the first request for data, receiving read data responsive to a read operation performed at the memory location of the memory array;
outputting the read data to the second controller;
error checking the read data at the memory device, wherein outputting the read data and error checking are performed in parallel;
setting, at the memory device, an open drain driver pin to indicate detection of a data error associated with the read data;
storing, at the memory device, error log information in response to a determination, based on the error checking, that the data error has occurred; and
sending a copy of the error log information to the second controller, wherein the error log information enables the second controller to correct the data error associated with the read data.

17. The method of claim 16 , wherein the error log information includes a read address associated with the memory location.

18. The method of claim 16 , wherein the error log information includes an error syndrome corresponding to the data error.

19. The method of claim 16 , wherein error correction code (ECC) bits associated with the data error.

20. The method of claim 16 , wherein the second controller is external to the memory device.

Assignees

• IBM

Inventors

• Coteus Paul W
• Hunter Hillery C
• Kilmer Charles A
• Kim Kyu-Hyoun
• Lastras-Montano Luis A
• Maule Warren E
• Patel Vipinchandra

Classifications

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F11/0772 Primary

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title