Integrated Assemblies having Conductive Material Along Three of Four Sides Around Active Regions, and Methods of Forming Integrated Assemblies

Patent metadata

Field	Value
Publication number	US-2021351087-A1
Application number	US-202016868133-A
Country	US
Kind code	A1
Filing date	May 6, 2020
Priority date	May 6, 2020
Publication date	Nov 11, 2021
Grant date	—

Abstract

Some embodiments include an integrated assembly having an array of vertically-extending active regions. Each of the active regions is contained within a four-sided area. Conductive gate material is configured as first conductive structures. Each of the first conductive structures extends along a row of the array. The first conductive structures include segments along three of the four sides of each of the four-sided areas. Second conductive structures are under the active regions and extend along columns of the array. Third conductive structures extend along the rows of the array and are adjacent the fourth sides of the four-sided areas. Storage-elements are coupled with the active regions. Some embodiments include methods of forming integrated assemblies.

First claim

I/We claim:

1 . An integrated assembly, comprising:
an array of vertically-extending active regions; each of the active regions being contained within a four-sided area; conductive gate material configured as first conductive structures; each of the first conductive structures extending along a row of the array; the first conductive structures comprising segments along three of the four sides of each of the four-sided areas, and not along the fourth side of each of the four-sided areas; second conductive structures under the active regions and extending along columns of the array; third conductive structures extending along the rows of the array and being adjacent the fourth sides of the four-sided areas; and storage-elements electrically coupled with the active regions.

2 . The integrated assembly of claim 1 wherein the active regions are four-sided polygons within the four-sided areas; and wherein the segments of the conductive structures are along only three of the sides of each of the four-sided polygons.

3 . The integrated assembly of claim 1 wherein the storage elements are capacitors.

4 . The integrated assembly of claim 3 wherein the capacitors are non-ferroelectric capacitors.

5 . The integrated assembly of claim 3 wherein the capacitors are ferroelectric capacitors.

6 . The integrated assembly of claim 1 wherein the third conductive structures are shield structures and are electrically coupled with a reference voltage node having a reference voltage.

7 . The integrated assembly of claim 6 wherein the reference voltage is within a range of from greater than or equal to ground to less than or equal to VCC.

8 . The integrated assembly of claim 1 wherein the active regions include body regions, and wherein the third conductive structures are electrically coupled with the body regions.

9 . The integrated assembly of claim 1 wherein the conductive gate material comprises metal.

10 . An integrated assembly, comprising:
an array of vertically-extending active regions; each of the active regions comprising a lower source/drain region, an upper source/drain region, and a channel region vertically between the upper and lower source/drain regions; each of the active regions being contained within a four-sided area; first conductive structures extending along rows of the array; the first conductive structures having comb-shaped configurations with shafts of the comb-shaped configurations extending linearly along the rows and being along first sides of the four-sided areas, and with teeth of the comb-shaped configurations projecting from the shafts and being along second and third sides of the four-sided areas; the comb-shaped configurations being adjacent the channel regions; second conductive structures under the active regions and extending along columns of the array; the second conductive structures being electrically coupled with the lower source/drain regions; and storage-elements electrically coupled with the upper source/drain regions.

11 . The integrated assembly of claim 10 further comprising third conductive structures extending along the rows of the array and being adjacent the fourth sides of the four-sided areas.

12 . The integrated assembly of claim 11 wherein the third conductive structures are shield structures and are electrically coupled with a reference voltage node having a reference voltage.

13 . The integrated assembly of claim 12 wherein the reference voltage is within a range of from greater than or equal to ground to less than or equal to VCC.

14 . The integrated assembly of claim 11 wherein the active regions include body regions, and wherein the third conductive structures are electrically coupled with the body regions.

15 . The integrated assembly of claim 10 wherein the storage elements are capacitors.

16 . The integrated assembly of claim 15 wherein the capacitors are non-ferroelectric capacitors.

17 . The integrated assembly of claim 15 wherein the capacitors are ferroelectric capacitors.

18 . The integrated assembly of claim 10 wherein the active regions are rectangular-shaped within the four-sided areas; wherein the shafts are along one of the sides of the rectangular-shaped active regions; and wherein the teeth are along second and third sides of the rectangular-shaped active regions.

19 . The integrated assembly of claim 10 wherein the comb-shaped configurations comprise tungsten.

20 . A method of forming an integrated assembly, comprising:
patterning an expanse of semiconductor material into a plurality of features which extend along a first direction; the features being spaced from one another by first trenches; forming steps within the first trenches and along bottom regions of the features; forming sacrificial material within the first trenches and over the steps; forming fill material over the sacrificial material to fill the first trenches; forming second trenches which extend along a second direction which crosses the first direction; the second trenches extending through the fill material, sacrificial material and steps, and at least partially through the semiconductor material to leave a remaining portion of the semiconductor material; the remaining portion of the semiconductor material including vertically-extending projections; each of the vertically-extending projections having a first side along one of the second trenches and a second side along another of the second trenches adjacent to said one of the second trenches; recessing the sacrificial material to form cavities between the steps and the fill material; the vertically-extending projections having exposed surfaces of the semiconductor material along the first and second sides and within the cavities; forming insulative material along the exposed surfaces of the semiconductor material of the vertically-extending projections; forming conductive material within the second trenches and over the insulative material, the conductive material being patterned as conductive structures extending along the first and second sides of the vertically-extending projections; forming third trenches to extend along the second direction and to extend at least partially through the vertically-extending projections; the third trenches dividing each of the vertically-extending projections into a pair of adjacent active regions; and forming storage-elements electrically coupled with the active regions.

21 . The method of claim 20 wherein:
the active regions are arranged in an array;
the conductive material is a second conductive material;
the conductive structures are second conductive structures extending along rows of the array;
the expanse of the semiconductor material is formed over a first conductive material; and
the first conductive is patterned into first conductive structures during the patterning of the expanse of the semiconductor material into the features, with the first conductive structures extending along columns of the array.

22 . The method of claim 21 wherein the expanse of the semiconductor material comprises an upper heavily-doped region, a lower heavily-doped region, and a central region between the upper and lower heavily-doped regions; wherein the upper and lower heavily-doped regions become upper and lower source/drain regions within the active regions; and wherein the central regions become channel regions within the active regions.

23 . The method of claim 22 where

Assignees

• Micron Technology Inc

Inventors

• Yang Litao
• Pulugurtha Srinivas
• Gao Yunfei
• Tang Sanh D
• Liu Haitao

Classifications

• H10P30/218

  characterised by the implantation in a compound semiconductor of both electrically active and inactive species in the same semiconductor region to be doped n-type or p-type · CPC title

• H10P30/206

  into Group III-V semiconductors · CPC title

• H10D30/025 Primary

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D86/011 Primary

  comprising FinFETs · CPC title