Mos transistor embedded substrate and switching power supply using the same

Patent metadata

Field	Value
Publication number	US-2020105677-A1
Application number	US-201916566874-A
Country	US
Kind code	A1
Filing date	Sep 11, 2019
Priority date	Sep 27, 2018
Publication date	Apr 2, 2020
Grant date	—

Abstract

Disclosed herein is a MOS transistor embedded substrate that includes first and second MOS transistors each having a source electrode formed on one surface and a drain electrode formed on other surface, and an insulation resin layer in which the first and second MOS transistors are embedded such that the source electrode of the first MOS transistor and the drain electrode of the second MOS transistor face a same direction and that the drain electrode of the first MOS transistor and the source electrode of the second MOS transistor face a same direction.

First claim

What is claimed is:

1 . A MOS transistor embedded substrate comprising:
first and second MOS transistors each having a source electrode formed on one surface and a drain electrode formed on other surface; and an insulation resin layer in which the first and second MOS transistors are embedded such that the source electrode of the first MOS transistor and the drain electrode of the second MOS transistor face a same direction and that the drain electrode of the first MOS transistor and the source electrode of the second MOS transistor face a same direction.

2 . The MOS transistor embedded substrate as claimed in claim 1 , further comprising:
a first terminal electrode connected to the source electrode of the first MOS transistor and the drain electrode of the second MOS transistor; a second terminal electrode connected to the drain electrode of the first MOS transistor; and a third terminal electrode connected to the source electrode of the second MOS transistor.

3 . The MOS transistor embedded substrate as claimed in claim 2 , further comprising a coupling wiring pattern connecting the source electrode of the first MOS transistor and the drain electrode of the second MOS transistor,
wherein the first terminal electrode is connected to the coupling wiring pattern.

4 . The MOS transistor embedded substrate as claimed in claim 3 , further comprising a first via conductor provided so as to penetrate the insulation resin layer,
wherein the first via conductor connects the coupling wiring pattern and the first terminal electrode.

5 . The MOS transistor embedded substrate as claimed in claim 4 , wherein the first via conductor is disposed between the first and second MOS transistors in a plan view.

6 . The MOS transistor embedded substrate as claimed in claim 2 , further comprising a first surface and a second surface positioned on an opposite side of the first surface,
wherein the first to third terminal electrodes are exposed on the first surface.

7 . The MOS transistor embedded substrate as claimed in claim 6 , further comprising a component mounting area on the second surface.

8 . The MOS transistor embedded substrate as claimed in claim 2 , further comprising:
a second via conductor provided so as to penetrate the insulation resin layer and to connect the drain electrode of the first MOS transistor and the second terminal electrode; and a third via conductor provided so as to penetrate the insulation resin layer and to connect the source electrode of the second MOS transistor and the third terminal electrode.

9 . A switching power supply comprising:
a MOS transistor embedded substrate including:
first and second MOS transistors each having a source electrode formed on one surface and a drain electrode formed on other surface; and
an insulation resin layer in which the first and second MOS transistors are embedded such that the source electrode of the first MOS transistor and the drain electrode of the second MOS transistor face a same direction and that the drain electrode of the first MOS transistor and the source electrode of the second MOS transistor face a same direction; and
a gate driver that supplies a drive signal to the gate electrodes of the respective first and second MOS transistors to turn ON the first and second MOS transistors in a mutually exclusive manner.

10 . The switching power supply as claimed in claim 9 , wherein the gate driver is mounted on the MOS transistor embedded substrate.

11 . The switching power supply as claimed in claim 9 , further comprising a boot strap capacitor connected between the first terminal electrode and the gate driver,
wherein the boot strap capacitor is mounted on the MOS transistor embedded substrate.

12 . An apparatus comprising:
a first insulation layer having first and second surfaces opposite to each other; a second insulation layer having third and fourth surfaces opposite to each other, the second insulation layer being stacked on the first insulation layer such that the fourth surface of the second insulation layer is in contact with the first surface of the first insulation layer; a first transistor having first and second electrodes, the first transistor is embedded in the first and second insulation layers such that the first electrode is covered with the fourth surface of the second insulation layer and that the second electrode is covered with the first surface of the first insulation layer; a second transistor having third and fourth electrodes, the second transistor is embedded in the first and second insulation layers such that the third electrode is covered with the fourth surface of the second insulation layer and that the fourth electrode is covered with the first surface of the first insulation layer; a first conductive pattern formed on the third surface of the second insulation layer; second and third conductive patterns formed on the second surface of the first insulation layer; a first via conductor provided so as to penetrate through the second insulation layer to connect the first electrode of the first transistor to the first conductive pattern; a second via conductor provided so as to penetrate through the second insulation layer to connect the third electrode of the second transistor to the first conductive pattern; a third via conductor provided so as to penetrate through the first insulation layer to connect the second electrode of the first transistor to the second conductive pattern; and a fourth via conductor provided so as to penetrate through the first insulation layer to connect the fourth electrode of the second transistor to the third conductive pattern.

13 . The apparatus as claimed in claim 12 , further comprising:
a fourth conductive pattern formed on the second surface of the first insulation layer; and a fifth via conductor provided so as to penetrate through the first and second insulation layers to connect the first conductive pattern to the fourth conductive pattern.

14 . The apparatus as claimed in claim 13 , wherein the fifth via conductor is arranged between the first and second transistors.

15 . The apparatus as claimed in claim 12 , further comprising:
fourth and fifth conductive patterns formed on the third surface of the second insulation layer; a fifth via conductor provided so as to penetrate through the first and second insulation layers to connect the second conductive pattern to the fourth conductive pattern; and a sixth via conductor provided so as to penetrate through the first and second insulation layers to connect the third conductive pattern to the fifth conductive pattern.

16 . The apparatus as claimed in claim 12 ,
wherein the first insulation layer includes first and second layers stacked on each other, wherein the first layer has a core material, and wherein the second layer is free from a core material.

17 . The apparatus as claimed in claim 12 ,
wherein each of the first electrode of the first transistor and the fourth electrode of the second transistor is a source electrode, and wherein each of the second electrode of the first transistor and the third electrode of the second transistor is a drain electrode.

Assignees

• Tdk Corp

Inventors

• Chiba Hironori
• Abe Toshiyuki

Classifications

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H01L23/5383

  Electricity · mapped topic

• H01L25/072

  Electricity · mapped topic

• H01L23/5386

  Electricity · mapped topic

• H01L23/5389 Primary

  Electricity · mapped topic