Alternative integration for redistribution layer process

Patent metadata

Field	Value
Publication number	US-2021193514-A1
Application number	US-201917263503-A
Country	US
Kind code	A1
Filing date	Jul 26, 2019
Priority date	Jul 26, 2018
Publication date	Jun 24, 2021
Grant date	—

Abstract

In one example, a method for redistribution layer (RDL) process is described. A substrate is provided. A dielectric layer is deposited on top of the substrate. The dielectric layer is patterned. A barrier and copper seed layer are deposited on top of the dielectric layer. A photoresist layer is applied on top of the barrier and copper seed layer. The photoresist layer is patterned to correspond with the dielectric layer pattern. Copper is electrodepositing in the patterned regions exposed by the photoresist layer. The photoresist layer is removed. The copper and seed barrier are etched.

First claim

What is claimed is:

1 . A method for redistribution layer (RDL) process, the method comprising:
depositing a dielectric layer on a surface of a substrate; patterning the dielectric layer, the patterned dielectric layer exposing a region of the surface of the substrate; depositing a protective layer on the patterned dielectric layer and the exposed region of the surface of the substrate; depositing a photoresist layer on the protective layer; patterning the photoresist layer, the patterned photoresist layer exposing a first region of the protective layer; electrodepositing a copper layer on top of the exposed first region of the protective layer; removing the patterned photoresist layer to expose a second region of the protective layer; and removing the exposed second region of the protective layer to expose the patterned dielectric layer.

2 . The method of claim 1 , further comprising:
removing the exposed patterned dielectric layer to expose a region of the surface of the substrate.

3 . The method of claim 1 , wherein a size of a feature in the patterned photoresist layer is larger than a size of a feature in the patterned dielectric layer.

4 . The method of claim 1 , wherein a size of a feature in the patterned photoresist layer is smaller than a size of a feature in the patterned dielectric layer.

5 . The method of claim 1 , wherein the protective layer comprises a barrier layer and a copper seed layer, the copper seed layer being on top of the barrier layer.

6 . The method of claim 1 , wherein the dielectric layer comprises a photosensitive polyimide layer or a nitride layer.

7 . The method of claim 6 , wherein patterning the dielectric layer further comprises:
forming the patterned dielectric layer using expose, develop, and descum processes.

8 . The method of claim 1 , wherein a feature size of the patterned photoresist layer matches a feature size of the underlying patterned dielectric layer.

9 . The method of claim 1 , wherein depositing the photoresist layer on top of the protective layer further comprises: filling features of the patterned dielectric layer with the photoresist layer.

10 . The method of claim 1 , wherein the photoresist layer lays on top of the features of the patterned dielectric layer and does not fill the features of the patterned dielectric layer.

Assignees

• Lam Res Corp

Inventors

• Oberst Justin
• Buckalew Bryan L
• Banik Stephen J

Classifications

• H10W72/01953

  by etching · CPC title

• H10W72/01931

  using blanket deposition · CPC title

• H10W72/01904

  using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates · CPC title

• H10W72/01235

  by plating, e.g. electroless plating or electroplating · CPC title

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title