Method of etching ferroelectric capacitor stack
US-9224592-B2 · Dec 29, 2015 · US
Memory device
US2021134814A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2021134814-A1 |
| Application number | US-202117147695-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jan 13, 2021 |
| Priority date | Sep 21, 2017 |
| Publication date | May 6, 2021 |
| Grant date | — |
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Abstract
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A memory device according to an embodiment includes a first conductive layer; a second conductive layer; a ferroelectric layer provided between the first conductive layer and the second conductive layer and containing hafnium oxide; a paraelectric layer provided between the first conductive layer and the ferroelectric layer and containing a first oxide; and an oxide layer provided between the paraelectric layer and the ferroelectric layer and containing a second oxide having an oxygen area density lower than an oxygen area density of the first oxide.
First claim
Opening claim text (preview).
What is claimed is: 1 . A memory device comprising: a first conductive layer; a second conductive layer; a ferroelectric layer provided between the first conductive layer and the second conductive layer and containing hafnium oxide; a paraelectric layer provided between the first conductive layer and the ferroelectric layer and containing a first oxide; and an oxide layer provided between the ferroelectric layer and the second conductive layer and containing a second oxide having an oxygen area density lower than an oxygen area density of hafnium oxide. 2 . The memory device according to claim 1 , wherein the first oxide is either silicon oxide or aluminum oxide. 3 . The memory device according to claim 1 , wherein a work function of the first conductive layer is greater than a work function of the second conductive layer. 4 . The memory device according to claim 1 , wherein the hafnium oxide contained in the ferroelectric layer includes third orthorhombic hafnium oxide. 5 . The memory device according to claim 1 , wherein the hafnium oxide contained in the ferroelectric layer contains at least one element selected from the group consisting of silicon (Si), titanium (Ti), zirconium (Zr), aluminum (Al), and yttrium (Y). 6 . A memory device comprising: a first conductive layer; a second conductive layer; a ferroelectric layer provided between the first conductive layer and the second conductive layer and containing hafnium oxide; a paraelectric layer provided between the first conductive layer and the ferroelectric layer and containing a first oxide; and an oxide layer provided between the first conductive layer and the paraelectric layer and containing a second oxide having an oxygen area density higher than an oxygen area density of the first oxide. 7 . The memory device according to claim 6 , wherein the first oxide is either silicon oxide or aluminum oxide. 8 . The memory device according to claim 6 , wherein a work function of the first conductive layer is greater than a work function of the second conductive layer. 9 . The memory device according to claim 6 , wherein the hafnium oxide contained in the ferroelectric layer includes third orthorhombic hafnium. 10 . The memory device according to claim 6 , wherein the hafnium oxide contained in the ferroelectric layer contains at least one element selected from the group consisting of silicon (Si), titanium (Ti), zirconium (Zr), aluminum (Al), and yttrium (Y). 11 . A memory device comprising: a first conductive layer; a second conductive layer; a ferroelectric layer provided between the first conductive layer and the second conductive layer and containing hafnium oxide; a paraelectric layer provided between the first conductive layer and the ferroelectric layer and containing a silicon oxide; and an oxide layer provided between the ferroelectric layer and the second conductive layer and containing at least one oxide selected from the group consisting of magnesium oxide, silicon oxide, germanium oxide, yttrium oxide, lutetium oxide, lanthanum oxide, and strontium oxide. 12 . The memory device according to claim 11 , wherein a work function of the first conductive layer is greater than a work function of the second conductive layer. 13 . The memory device according to claim 11 , wherein the hafnium oxide contained in the ferroelectric layer includes third orthorhombic hafnium oxide. 14 . The memory device according to claim 11 , wherein the hafnium oxide contained in the ferroelectric layer contains at least one element selected from the group consisting of silicon (Si), titanium (Ti), zirconium (Zr), aluminum (Al), and yttrium (Y). 15 . A memory device comprising: a first conductive layer; a second conductive layer; a ferroelectric layer provided between the first conductive layer and the second conductive layer and containing hafnium oxide; a paraelectric layer provided between the first conductive layer and the ferroelectric layer and containing a silicon oxide; and an oxide layer provided between the first conductive layer and the paraelectric layer and containing at least one oxide selected from the group consisting of aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, and magnesium oxide. 16 . The memory device according to claim 15 , wherein a work function of the first conductive layer is greater than a work function of the second conductive layer. 17 . The memory device according to claim 15 , wherein the hafnium oxide contained in the ferroelectric layer includes third orthorhombic hafnium oxide. 18 . The memory device according to claim 15 , wherein the hafnium oxide contained in the ferroelectric layer contains at least one element selected from the group consisting of silicon (Si), titanium (Ti), zirconium (Zr), aluminum (Al), and yttrium (Y).
Assignees
Inventors
Classifications
having ferroelectric layers · CPC title
using ferroelectric capacitors · CPC title
Electricity · mapped topic
Electricity · mapped topic
- H01L27/11507Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US2021134814A1 cover?
- A memory device according to an embodiment includes a first conductive layer; a second conductive layer; a ferroelectric layer provided between the first conductive layer and the second conductive layer and containing hafnium oxide; a paraelectric layer provided between the first conductive layer and the ferroelectric layer and containing a first oxide; and an oxide layer provided between the p…
- Who is the assignee on this patent?
- Toshiba Memory Corp
- What technology area does this patent fall under?
- Primary CPC classification H01L27/11507. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu May 06 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).