Semiconductor structure

Patent metadata

Field	Value
Publication number	US-2021134783-A1
Application number	US-202016858293-A
Country	US
Kind code	A1
Filing date	Apr 24, 2020
Priority date	Oct 30, 2019
Publication date	May 6, 2021
Grant date	—

Abstract

A semiconductor structure includes a first cell and a second cell. The second cell vertically abuts the first cell. Each first cell has a plurality of first active regions. Each first active region has a first vertical height. Each second cell has a plurality of second active regions. Each second active region has a second vertical height. The second vertical height is different from the first vertical height.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a first cell comprising:
a first boundary polysilicon section and a second boundary polysilicon section;
a first gate polysilicon section disposed between the first boundary polysilicon section and the second boundary polysilicon section, and the first gate polysilicon section separated from the first boundary polysilicon section and the second boundary polysilicon section;
a plurality of first active regions disposed between the first boundary polysilicon section and the first gate polysilicon section, and connected to the first boundary polysilicon section and the first gate polysilicon section, and disposed between the second boundary polysilicon section and the first gate polysilicon section, and connected to the second boundary polysilicon section and the first gate polysilicon section, each first active region having a first vertical height; and
a second cell vertically abutting the first cell, comprising:
a third boundary polysilicon section and a fourth boundary polysilicon section;
a second gate polysilicon section disposed between the third boundary polysilicon section and the fourth boundary polysilicon section, and the second gate polysilicon section separated from the third boundary polysilicon section and the fourth boundary polysilicon section;
a plurality of second active regions disposed between the third. boundary polysilicon section and the second gate polysilicon section, and connected to the third boundary polysilicon section and the second gate polysilicon section, and disposed between the fourth boundary polysilicon section and the second gate polysilicon section, and connected to the fourth boundary polysilicon section and the second gate polysilicon section, each second active region having a second vertical height;
the second vertical height is different from the first vertical height.

2 . The semiconductor structure of claim 1 , wherein the first vertical height is a multiple of fin number, and the second vertical height is a multiple of fin number.

3 . The semiconductor structure of claim 1 , further comprising a third cell vertically abutting the first cell or the second cell, a third active region of the third cell having a third vertical height, and the third vertical height being different from the first vertical height and the second vertical height.

4 . The semiconductor structure of claim 1 , further comprising a first track cell and a second track cell respectively disposed above the first cell and the second cell, the first track cell having a first amount of first tracks, and the second track cell having a second amount of second tracks, wherein the first amount is different from the second amount.

5 . The semiconductor structure of claim 4 , wherein the first tracks in the first track cell and the second tracks in the second track cell are parallel to the first active regions and the second active regions, the first track cell and the second track cell are disposed on a metal-n layer.

6 . The semiconductor structure of claim 5 , further comprising a third track cell vertically abuts the first track cell or the second track cell, the third track cell having a third amount of third tracks, the third amount is different from the first amount and the second amount.

7 . The semiconductor structure of claim 5 , further comprising a metal line electrically connecting to the first tracks or the second track, the metal line is disposed on a metal-n+1 layer.

8 . The semiconductor structure of claim 1 , wherein the first boundary polysilicon section is connected to the third boundary polysilicon section to form a first boundary polysilicon segment, the second polysilicon section is connected to the fourth boundary polysilicon section to form a second boundary polysilicon segment, and the first gate polysilicon section is connected to the second gate polysilicon section to form a gate polysilicon segment.

9 . The semiconductor structure of claim 8 , wherein the first cell and the second cell are formed as a cell group.

10 . A semiconductor structure, comprising:
a plurality of cell columns, each cell column having a plurality of first cells and a plurality of second cells, the second cell vertically abutting the first cell, each cell column comprising: a first boundary poi con strap and a second boundary polysilicon strap; a gate polysilicon strap disposed between the first boundary polysilicon strap and the second boundary polysilicon strap, and the gate polysilicon strap separated from the first boundary polysilicon strap and the second boundary polysilicon strap; a plurality of first active regions disposed in the first cells, and disposed between the first boundary polysilicon strap and the gate polysilicon strap, and connected to the first boundary polysilicon strap and the gate polysilicon strap, and disposed between the second boundary polysilicon strap and the gate polysilicon strap, and connected to the second boundary polysilicon strap and the gate polysilicon strap, each first active region having a first vertical height; and a plurality of second active regions disposed in the second cells, and disposed between the first boundary polysilicon strap and the gate polysilicon strap, and connected to the first boundary polysilicon strap and the gate polysilicon strap, and disposed between the second boundary polysilicon strap and the polysilicon strap, and connected to the second boundary polysilicon strap and the gate polysilicon strap, each second active region having a second vertical height; wherein the second vertical height is different from the first vertical height.

11 . The semiconductor structure of claim 10 , wherein the first cells vertically abut, and the second cells vertically abut, one of the second cells vertically abuts one of the first cells.

12 . The semiconductor structure of claim 10 , wherein the cell columns are arranged with the same horizontal level.

13 . The semiconductor structure of claim 10 , further comprising a plurality of track columns, disposed above the cell columns, the track columns are disposed on a metal-n layer.

14 . The semiconductor structure of claim 13 , wherein each track column comprises a plurality of first track cells and a plurality of second track cells, the first track cells are disposed above the first cells, and the second track cells are disposed above the second cells, the first track cell has a plurality of first tracks, the second track cell has a plurality of second tracks, the number of the first tracks is different from that of the second tracks.

15 . The semiconductor structure of claim 13 , wherein the track columns are arranged with the same horizontal level.

16 . A semiconductor structure, comprising:
an active layer, having a plurality of first cells and a plurality of second cells, the second cell vertically abutting the first cell, each first cell having a plurality of first active regions, each first active region having a first vertical height; each second cell having a plurality of second active regions, each second active region having a second vertical height, the second vertical height being different from the first vertical height; a metal-n layer, disposed above the active layer, the metal-n layer having a plurality of first track cells and a plurality of second track cells respectively disposed above the first cells and the second cells, the first track cell having a first amount of first tracks, and the second track cell having a second amount of second tracks, the first amount being diff

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Li Jian-Sing
• Lu Chi-Yu
• Zhuang hui-zhong
• Chen Chih-Liang

Classifications

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D84/962

  Horizontal or vertical grid line density · CPC title

• H10D84/959

  Connectability characteristics, i.e. diffusion and polysilicon geometries · CPC title

• H10D84/907

  CMOS gate arrays · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title