Inter-layer slot for increasing printed circuit board power performance

Patent metadata

Field	Value
Publication number	US-2021127479-A1
Application number	US-202017081916-A
Country	US
Kind code	A1
Filing date	Oct 27, 2020
Priority date	Oct 28, 2019
Publication date	Apr 29, 2021
Grant date	—

Abstract

A printed circuit board includes a first voltage plane disposed on a first surface of a first electrically insulating layer and a second voltage plane. An inter-layer slot that is formed through the first electrically insulating layer and includes an electrically conductive material electrically couples the first voltage plane to the second voltage plane.

First claim

What is claimed is:

1 . A printed circuit board, comprising:
a first voltage plane disposed on a first surface of a first electrically insulating layer; and a second voltage plane, wherein an inter-layer slot that is formed through the first electrically insulating layer and includes an electrically conductive material electrically couples the first voltage plane to the second voltage plane.

2 . The printed circuit board of claim 1 , wherein the second voltage plane is disposed on a second surface of the first electrically insulating layer.

3 . The printed circuit board of claim 1 , further comprising a second electrically insulating layer, wherein the second voltage plane is disposed on a first surface of the second electrically insulating layer.

4 . The printed circuit board of claim 3 , wherein the inter-layer slot also is formed through the second electrically insulating layer.

5 . The printed circuit board of claim 1 , wherein the electrically conductive material comprises electroplated copper.

6 . The printed circuit board of claim 5 , wherein the electroplated copper substantially fills the inter-layer slot.

7 . The printed circuit board of claim 1 , wherein the first voltage plane comprises a ground plane or a power plane.

8 . The printed circuit board of claim 7 , wherein the power plane is configured to be electrically coupled to a power source when the power source is mounted on the printed circuit board, and wherein the power plane is further configured to be electrically coupled to an integrated circuit when the integrated circuit is mounted on the printed circuit board.

9 . The printed circuit board of claim 7 , wherein the ground plane is configured to be electrically coupled to a first integrated circuit when the integrated circuit is mounted on the printed circuit board.

10 . The printed circuit board of claim 9 , wherein the ground plane is configured to be electrically coupled to a second integrated circuit when the integrated circuit is mounted on the printed circuit board.

11 . The printed circuit board of claim 1 , further comprising a plurality of signal traces disposed on a second surface of the first electrically insulating layer and configured to be electrically coupled to an integrated circuit when the integrated circuit is mounted on the printed circuit board.

12 . The printed circuit board of claim 1 , wherein the inter-layer slot comprises a plurality of overlapping holes formed through the first electrically insulating layer.

13 . The printed circuit board of claim 12 , wherein each overlapping hole included in the plurality of overlapping holes overlaps an adjacent hole also included in the plurality of overlapping holes by at least about 50% of the diameter of the adjacent hole.

14 . A method for manufacturing a printed circuit board, the method comprising:
forming an inter-layer slot through a first layer of electrically insulating material via a plurality of overlapping holes formed through the first layer of electrically insulating layer; depositing an electrically conductive material within the inter-layer slot; forming a first voltage plane on a first surface of the first layer; and forming a second voltage plane that is electrically coupled to the first voltage plane via the electrically conductive material within the inter-layer slot.

15 . The method of claim 14 , further comprising forming the plurality of overlapping holes via one of a laser ablation process, a mechanical drilling process, or a mechanical routing process.

16 . The method of claim 14 , wherein depositing the electrically conductive material within the inter-layer slot comprises substantially filling the inter-layer slot with electroplated copper.

17 . The method of claim 14 , further comprising forming a second layer of electrically insulating material, wherein the second voltage plane is formed on a second surface of the second layer.

18 . The method of claim 17 , further comprising forming the inter-layer slot in the second layer.

19 . The method of claim 18 , wherein the inter-layer slot is formed in the first layer and in the second layer in a single material removal process.

20 . The method of claim 18 , wherein the inter-layer slot is formed in the first layer in a first material removal process and the inter-layer slot is formed in the second layer in a second material removal process.

Assignees

• Nvidia Corp

Inventors

• Yu Mingyi
• Attaluri Ananta H
• Bodi Gregory Patrick
• Capillo Jr Carmen A
• Warner Michael James

Classifications

• H05K3/423

  characterised by electroplating method · CPC title

• H05K1/0265 Primary

  characterized by the lay-out of or details of the printed conductors, e.g. reinforced conductors, redundant conductors, conductors having different cross-sections · CPC title

• H05K2201/09981

  Metallised walls · CPC title

• H05K2201/09336

  Signal conductors in same plane as power plane · CPC title

• H05K2201/09309

  Core having two or more power planes; Capacitive laminate of two power planes · CPC title