Domino full adder based on delayed gating positive feedback

Patent metadata

Field	Value
Publication number	US-2021109710-A1
Application number	US-202017069834-A
Country	US
Kind code	A1
Filing date	Oct 13, 2020
Priority date	Oct 14, 2019
Publication date	Apr 15, 2021
Grant date	—

Abstract

A domino full adder based on delayed gating positive feedback comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a first inverter, a second inverter, a third inverter and a fourth inverter.

First claim

What is claimed is:

1 . A domino full adder based on delayed gating positive feedback, the domino full adder comprising:
a first PMOS (P-type metal-oxide-silicon) transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS (N-type metal-oxide-silicon) transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a first inverter, a second inverter, a third inverter and a fourth inverter, wherein a source of the first PMOS transistor, a source of the second PMOS transistor, a source of the fourth PMOS transistor, a source of the fifth PMOS transistor, a source of the seventh PMOS transistor and a source of the eighth PMOS transistor are connected, a connecting terminal is a power terminal of the domino full adder, and an external power supply is accessed to the power terminal of the domino full adder; a gate of the first PMOS transistor, a gate of the first NMOS transistor, a gate of the fourth PMOS transistor, a gate of the fourth NMOS transistor, a gate of the seventh PMOS transistor, a gate of the eleventh NMOS transistor and an input terminal of the second inverter are connected, a connecting terminal is a clock terminal of the domino full adder, and an external clock signal is accessed to the clock terminal of the domino full adder; a drain of the first PMOS transistor, a drain of the first NMOS transistor, a drain of the third PMOS transistor and an input terminal of the first inverter are connected; a gate of the second PMOS transistor, a source of the second NMOS transistor, a gate of the third NMOS transistor and a gate of the seventh NMOS transistor are connected, a connecting terminal is a first input terminal of the domino full adder, and a first addend signal is accessed to the first input terminal of the domino full adder; a drain of the second PMOS transistor and a source of the third PMOS transistor are connected; a gate of the third PMOS transistor, a gate of the second NMOS transistor, a source of the third NMOS transistor and a gate of the eighth NMOS transistor are connected, a connecting terminal is a second input terminal of the domino full adder, and a second addend signal is accessed to the second input terminal of the domino full adder; a drain of the fourth PMOS transistor, a drain of the fifth NMOS transistor, a drain of the sixth PMOS transistor, a drain of the seventh NMOS transistor and an input terminal of the third inverter are connected; a drain of the fifth PMOS transistor and a source of the sixth PMOS transistor are connected; a gate of the fifth PMOS transistor and an output terminal of the third inverter are connected, a connecting terminal is an upper-bit carry signal output terminal of the domino full adder, and the upper-bit carry signal output terminal of the domino full adder outputs a carry signal to an upper bit; a gate of the sixth PMOS transistor and an output terminal of the second inverter are connected; a drain of the seventh PMOS transistor, a drain of the eleventh NMOS transistor, a drain of the ninth PMOS transistor and an input terminal of the fourth inverter are connected; a drain of the eighth PMOS transistor and a source of the ninth PMOS transistor are connected; a gate of the eighth PMOS transistor, a gate of the fifth NMOS transistor, a gate of the ninth NMOS transistor and a source of the tenth NMOS transistor are connected, a connecting terminal is a lower-bit carry signal input terminal of the domino full adder, and a lower-bit carry signal is accessed to the lower-bit carry signal input terminal of the domino full adder; a gate of the ninth PMOS transistor, a source of the ninth NMOS transistor, a gate of the tenth NMOS transistor, a gate of the sixth NMOS transistor and an output terminal of the first inverter are connected; a source of the first NMOS transistor, a drain of the second NMOS transistor and a drain of the third NMOS transistor are connected; a drain of the fourth NMOS transistor, a source of the sixth NMOS transistor and a source of the eighth NMOS transistor are connected; a source of the fourth NMOS transistor is grounded; a source of the fifth NMOS transistor and a drain of the sixth NMOS transistor are connected; a source of the seventh NMOS transistor and a drain of the eighth NMOS transistor are connected; a drain of the ninth NMOS transistor, a drain of the tenth NMOS transistor and a source of the eleventh NMOS transistor are connected; and an output terminal of the fourth inverter is a sum signal output terminal of the domino full adder, and the sum signal output terminal of the domino full adder outputs a sum signal.

Assignees

• Univ Ningbo

Inventors

• Wang Pengjun
• Zhang Xiaotian
• Zhang Huihong
• Zhang Yuejun
• Yu Haizhen

Classifications

• G06F7/505

  in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination · CPC title

• H03K19/0948 Primary

  using CMOS {or complementary insulated gate field-effect transistors} · CPC title

• H03K19/00323

  Delay compensation · CPC title

• G06F7/507 Primary

  using selection between two conditionally calculated carry or sum values · CPC title

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title