Semiconductor device configured for gate dielectric monitoring

Patent metadata

Field	Value
Publication number	US-2021072304-A1
Application number	US-202016996458-A
Country	US
Kind code	A1
Filing date	Aug 18, 2020
Priority date	Sep 9, 2019
Publication date	Mar 11, 2021
Grant date	—

Abstract

The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices including a metal-oxide-semiconductor (MOS) transistor and are configured for accelerating and monitoring degradation of the gate dielectric of the MOS transistor. In one aspect, a semiconductor device configured with gate dielectric monitoring capability comprises a metal-oxide-semiconductor (MOS) transistor including a source, a drain, a gate, and a backgate region formed in a semiconductor substrate. The semiconductor device additionally comprises a bipolar junction transistor (BJT) including a collector, a base, and an emitter formed in the semiconductor substrate, wherein the backgate region of the MOS transistor serves as the base of the BJT and is independently accessible for activating the BJT. The MOS transistor and the BJT are configured to be concurrently activated by biasing the backgate region independently from the source of the MOS transistor, such that the base of the BJT injects carriers of a first charge type into the backgate region of the MOS transistor, where the first charge type is opposite charge type to channel current carriers.

First claim

1 . A semiconductor device configured with gate dielectric monitoring capability, the semiconductor device comprising:
a metal-oxide-semiconductor (MOS) transistor including a source, a drain, a gate, and a backgate region formed in a semiconductor substrate; and a bipolar junction transistor (BJT) including a collector, a base, and an emitter formed in the semiconductor substrate, wherein the backgate region of the MOS transistor serves as the base of the BJT and is independently accessible for activating the BJT, wherein the MOS transistor and the BJT are configured to be concurrently activated by biasing the backgate region independently from the source of the MOS transistor, such that the base of the BJT injects carriers of a first charge type into the backgate region of the MOS transistor, the first charge type being opposite charge type to channel current carriers.

2 . The semiconductor device of claim 1 , wherein the MOS transistor is a lateral double-diffused MOS (LDMOS) transistor comprising an extended drain drift drain region formed in the semiconductor substrate laterally between the drain and a channel of the LDMOS transistor and covered by a field oxide, wherein the extended drain drift region is doped with the same dopant type at a lower concentration compared to the drain, and wherein a gate dielectric extends partly into the extended drain draft region.

3 . The semiconductor device of claim 2 , wherein the field oxide is a locally oxidized silicon (LOCOS), and wherein the field oxide abuts the gate dielectric over the extended drain drift region.

4 . The semiconductor device of claim 2 , wherein the LDMOS transistor is an n-channel LDMOS (nLDMOS) transistor and the BJT is an NPN BJT such that the carriers of the first charge type injected into the backgate region are holes when the MOS transistor and the BJT are concurrently activated.

5 . The semiconductor device of claim 4 , further comprising:
a first contact electrically connected to the source and configured for applying a source voltage (V s ) to the source; and a second contact electrically connected to the backgate region and configured for applying a backgate voltage (V bg ) to the backgate region, wherein the semiconductor device is configured to be interchangeably operated between an accelerated stress mode in which the BJT is activated and a product mode in which the BJT is unactivated.

6 . The semiconductor device of claim 5 , wherein the semiconductor device is configured such that the BJT is activated by applying a positive backgate voltage to the second contact, and wherein when the nLDMOS transistor and the NPN BJT are concurrently activated, a concentration of holes in the backgate region increases by at least two orders of magnitude relative to the backgate region prior to concurrently activating the nLDMOS transistor and the NPN BJT.

7 . The semiconductor device of claim 6 , wherein the semiconductor device is configured such that holes generated in the backgate region are injected into a portion of a gate dielectric of the nLDMOS transistor that is vertically over the backgate region and laterally between the field oxide and the channel of the nLDMOS transistor.

8 . The semiconductor device of claim 7 , wherein the backgate region is configured to be biased through a dedicated contact formed thereon.

9 . The semiconductor device of claim 7 , wherein the backgate region is configured to be electrically floating.

10 . A semiconductor device comprising a double diffused metal-oxide-semiconductor (DMOS) transistor and a bipolar junction transistor (BJT) formed in a semiconductor substrate, wherein a well of a first type serving both as a backgate region of the DMOS transistor and as a base of the BJT is configured to be biased independently through a separate well contact, wherein the DMOS transistor and the BJT are configured to be concurrently activated by biasing the backgate region independently from a source of the DMOS transistor.

11 . The semiconductor device of claim 10 , wherein the DMOS transistor is a n-type lateral DMOS (nLDMOS) transistor comprising an extended drain drift drain region formed in the semiconductor substrate laterally between a drain and a channel of the nLDMOS and covered by a field oxide, wherein the a gate dielectric extends partly into the extended drain draft region.

12 . The semiconductor device of claim 11 , wherein the field oxide is a locally oxidized silicon (LOCOS), and wherein the field oxide abuts the gate dielectric over the extended drain drift region.

13 . The semiconductor device of claim 11 , wherein the semiconductor device is configured to be interchangeably operated between an accelerated stress mode in which the BJT is activated and a product mode in which the BJT is unactivated, wherein in the accelerated stress mode, the semiconductor device is configured to accelerate degradation of the gate dielectric compared to the product mode by injecting holes into the gate dielectric.

14 . The semiconductor device of claim 13 , wherein in the accelerated stress mode, the holes that are injected into the gate dielectric are supplied from the backgate region of the nLDMOS transistor.

15 . The semiconductor device of claim 11 , wherein the BJT is an NPN BJT, wherein a source of the nLDMOS transistor serves as an emitter of the BJT, and wherein a drain of the nLDMOS transistor serves as a collector of the BJT.

16 . The semiconductor device of claim 13 , further comprising:
a first contact electrically connected to the source and configured for applying a source voltage (V s ) to the source; and a second contact electrically connected to the backgate region and configured for applying a backgate voltage (V bg ) to the backgate region, wherein the semiconductor device is configured such that the BJT is activated by applying a positive backgate voltage to the second contact, and wherein upon the activation of the BJT in the accelerated stress mode, a concentration of holes in the backgate region increases by at least two orders of magnitude relative to the backgate region prior to the activation of the BJT in the product mode.

17 . The semiconductor device of claim 16 , wherein the semiconductor device is configured such that in the product mode, the V s and the V bg having the same magnitude are applied, whereas in the accelerated stress mode, the V s and the V bg having different magnitudes are applied.

18 . The semiconductor device of claim 10 , wherein the backgate region is configured to be biased through a dedicated contact formed thereon.

19 . The semiconductor device of claim 10 , wherein the backgate region is configured to be electrically floating.

20 . A method of monitoring a gate dielectric of a metal-oxide-semiconductor (MOS) transistor, the method comprising:
providing a semiconductor device comprising a metal-oxide-semiconductor (MOS) transistor and a bipolar junction transistor (BJT), wherein a backgate region of the MOS transistor serving as a base of the BJT is independently accessible for activating the BJT; and concurrently activating the MOS transistor and the BJT by biasing the backgate region independently from the source of the MOS transistor, such that the base of the BJT injects carriers of a first charge type into the backgate region of the MOS transistor, the first charge type being opposite charge type to channel current carriers.

21 . (canceled)

22 . (canceled)

23 . (canceled)

Assignees

• Analog Devices International Unlimited Co

Inventors

• Coyne Edward John
• Meskell John P
• Heffernan Colm Patrick
• Forde Mark
• Geary Shane

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10D84/409

  Combinations of FETs or IGBTs with lateral BJTs and with one or more of diodes, resistors or capacitors · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D30/65

  Lateral DMOS [LDMOS] FETs · CPC title

• H10D10/60

  Lateral BJTs · CPC title