Multilayer wiring forming method and recording medium

US2020395243A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2020395243-A1
Application numberUS-201916971450-A
CountryUS
Kind codeA1
Filing dateFeb 7, 2019
Priority dateFeb 21, 2018
Publication dateDec 17, 2020
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A multilayer wiring forming method includes filling a via, which is formed in an insulating film including an oxide film formed on a wiring of a substrate and is extended to the wiring, by forming an electroless plating film, which does not diffuse into the oxide film, from a bottom surface of the via while using the wiring, which is exposed at the bottom surface of the via, as a catalyst.

First claim

Opening claim text (preview).

1 . A multilayer wiring forming method, comprising: filling a via, which is formed in an insulating film including an oxide film formed on a wiring of a substrate and is extended to the wiring, by forming an electroless plating film, which does not diffuse into the oxide film, from a bottom surface of the via while using the wiring, which is exposed at the bottom surface of the via, as a catalyst. 2 . The multilayer wiring forming method of claim 1 , wherein the wiring contains Co, Ni or Ru. 3 . A multilayer wiring forming method, comprising: filling a via, which is formed in an insulating film including an oxide film formed on a wiring of a substrate and is extended to the wiring, by forming an electroless plating film, which does not diffuse into the oxide film, from a bottom surface of the via while using a barrier film, which is exposed at the bottom surface of the via, as a catalyst. 4 . The multilayer wiring forming method of claim 3 , wherein the wiring contains Cu. 5 . The multilayer wiring forming method of claim 1 , wherein the electroless plating film contains Co and W. 6 . The multilayer wiring forming method of claim 5 , wherein the electroless plating film contains 1 at % to 20 at % of W, and a rest of the electroless plating film is made of Co and an inevitable impurity. 7 . The multilayer wiring forming method of claim 1 , wherein the electroless plating film contains Ni. 8 . A computer-readable recording medium having stored thereon computer-executable instructions that, in response to execution, cause a multilayer wiring forming system to perform a multilayer wiring forming method as claimed in claim 1 .

Assignees

Inventors

Classifications

  • of insulating materials · CPC title

  • H10P14/46Primary

    using a liquid · CPC title

  • Insulating materials thereof · CPC title

  • for electroless plating · CPC title

  • the principal metal being a transition metal · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2020395243A1 cover?
A multilayer wiring forming method includes filling a via, which is formed in an insulating film including an oxide film formed on a wiring of a substrate and is extended to the wiring, by forming an electroless plating film, which does not diffuse into the oxide film, from a bottom surface of the via while using the wiring, which is exposed at the bottom surface of the via, as a catalyst.
Who is the assignee on this patent?
Tokyo Electron Ltd
What technology area does this patent fall under?
Primary CPC classification H10P14/46. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Dec 17 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).