Hardware processors and methods for extended microcode patching

Patent metadata

Field	Value
Publication number	US-2020348939-A1
Application number	US-202016932682-A
Country	US
Kind code	A1
Filing date	Jul 17, 2020
Priority date	Dec 29, 2018
Publication date	Nov 5, 2020
Grant date	—

Abstract

Hardware processors and methods for extended microcode patching through on-die and off-die secure storage are described. In one embodiment, the additional storage resources used for storing micro-operations are section(s) of a cache that are unused at runtime and/or unused by a configuration of a processor. For example, the additional storage resources may be a section of a cache that is used to store context information from a core when the core is transitioned to a power state that shuts off voltage to the core. Non-limiting examples of such sections are one or more sections for storage of context information for a transition of a thread to idle or off, storage of context information for a transition of a core for a multiple core processor to idle or off, or storage of coherency information for a transition of a cache coherency circuit (e.g., cache box (CBo)) to idle or off.

First claim

What is claimed is:

1 . A processor comprising:
an execution circuit to execute micro-operations; a cache; and a microcode sequencer comprising a patch memory, wherein the microcode sequencer is to:
determine that an instruction requested for execution is to be patched,
cause execution of patch code by the execution circuit to load a patch set of at least one micro-operation for the instruction that is to be patched into the patch memory from the cache, and
cause execution of the patch set of at least one micro-operation for the instruction from the patch memory by the execution circuit.

2 . The processor of claim 1 , wherein the cache comprises a section to store context information from a core comprising the execution circuit when the core is transitioned to a power state that shuts off voltage to the core.

3 . The processor of claim 2 , wherein the power state is a C6 power state according to an Advanced Configuration and Power Interface (ACPI) standard.

4 . The processor of claim 2 , wherein the patch set of at least one micro-operation for the instruction is to be loaded into the patch memory from a previously unused section of the cache separate from the section of the cache to store context information.

5 . The processor of claim 2 , wherein the patch set of at least one micro-operation for the instruction is to be loaded into the patch memory from the section of the cache to store context information, and the microcode sequencer is to, for the patch set of at least one micro-operation to be stored in a system memory coupled to the processor, cause execution of code by the execution circuit that loads the patch set of at least one micro-operation into the section of the cache from the system memory.

6 . The processor of claim 1 , wherein the cache is not user accessible.

7 . The processor of claim 1 , wherein the microcode sequencer is to cause the execution of the patch code from the patch memory.

8 . The processor of claim 1 , wherein firmware, in non-transitory storage coupled to the processor, comprises an instruction that when decoded and executed by the processor is to cause the processor to store the patch set of at least one micro-operation into the cache.

9 . The processor of claim 1 , wherein, when the patch set of at least one micro-operation loaded into the patch memory overwrites at least one of a plurality of micro-operations stored in the patch memory, the microcode sequencer is to reload the at least one of the plurality of micro-operations that was overwritten when execution of the patch set of at least one micro-operation is complete.

10 . The processor of claim 1 , wherein the microcode sequencer is to cause, for a second instruction requested for execution, a second patch set of at least one micro-operation, different than the patch set, to be loaded into the patch memory from the cache, and execution of the second patch set of at least one micro-operation for the second instruction from the patch memory by the execution circuit.

11 . A method comprising:
receiving a request to execute an instruction with a processor; determining, by a microcode sequencer of the processor, that the instruction requested for execution is to be patched; causing, by the microcode sequencer of the processor, execution of patch code to load a patch set of at least one micro-operation for the instruction that is to be patched into a patch memory of the microcode sequencer from a cache of the processor; sending, by the microcode sequencer of the processor, the patch set of at least one micro-operation from the patch memory to an execution circuit of the processor; and executing the patch set of at least one micro-operation for the instruction with the execution circuit of the processor.

12 . The method of claim 11 , wherein the method further comprises storing context information from a core comprising the execution circuit in a section of the cache when the core is transitioned to a power state that shuts off voltage to the core.

13 . The method of claim 12 , wherein the power state is a C6 power state according to an Advanced Configuration and Power Interface (ACPI) standard.

14 . The method of claim 12 , wherein the load of the patch set comprises loading the patch set of at least one micro-operation for the instruction into the patch memory of the microcode sequencer from a previously unused section of the cache separate from the section of the cache to store context information.

15 . The method of claim 12 , wherein the load of the patch set comprises loading the patch set of at least one micro-operation for the instruction into the patch memory of the microcode sequencer from the section of the cache to store context information.

16 . The method of claim 11 , wherein the cache is not user accessible.

17 . The method of claim 11 , wherein the method further comprises storing the patch code into the patch memory, and the causing execution comprises sending the patch code from the patch memory to the execution circuit.

18 . The method of claim 11 , wherein the method further comprises storing firmware including an instruction in non-transitory storage coupled to the processor, and executing the instruction from the firmware by the processor to cause storing of the patch set of at least one micro-operation into the cache.

19 . The method of claim 11 , wherein, when the load of the patch set of at least one micro-operation into the patch memory overwrites at least one of a plurality of micro-operations stored in the patch memory, the method further comprises reloading, by the microcode sequencer, the at least one of the plurality of micro-operations that were overwritten when execution of the patch set of at least one micro-operation is complete.

20 . The method of claim 11 , wherein the method further comprises:
receiving a request to execute a second instruction with the processor; determining, by the microcode sequencer of the processor, that the second instruction requested for execution is to be patched; causing, by the microcode sequencer of the processor, execution of the patch code to load a second patch set of at least one micro-operation for the second instruction that is to be patched into the patch memory of the microcode sequencer from the cache; sending, by the microcode sequencer of the processor, the second patch set of at least one micro-operation from the patch memory to the execution circuit of the processor; and executing the second patch set of at least one micro-operation for the second instruction with the execution circuit of the processor.

21 . A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:
receiving a request to execute an instruction with a processor; determining, by a microcode sequencer of the processor, that the instruction requested for execution is to be patched; causing, by the microcode sequencer of the processor, execution of patch code to load a patch set of at least one micro-operation for the instruction that is to be patched into a patch memory of the microcode sequencer from a cache of the processor; sending, by the microcode sequencer of the processor, the patch set of at least one micro-operation from the patch memory to an execution circuit of the processor; and executing the patch set of at least one micro-operation for the instruction with the execution circuit of the processor.

Assignees

• Intel Corp

Inventors

• Ghetie Sergiu D

Classifications

• G06F9/268 Primary

  Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs · CPC title

• G06F9/24 Primary

  Loading of the microprogram · CPC title

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title